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SamTebbs33SamTebbs33
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[AArch64][NFC] Use regexes in register class tests
Some MIR and IR tests include checks for register class IDs, which are unnecessary since the register class name is also checked for and that doesn't change when new classes are added. This patch replaces the hard-coded register class ID checks with regexes so they don't have to be updated every time a new class is added.
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6 files changed

+31
-31
lines changed

6 files changed

+31
-31
lines changed

‎llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ define void @asm_simple_register_clobber() {
2626
define i64 @asm_register_early_clobber() {
2727
; CHECK-LABEL: name: asm_register_early_clobber
2828
; CHECK: bb.1 (%ir-block.0):
29-
; CHECK-NEXT: INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, 2752523 /* regdef-ec:GPR64common */, def early-clobber %0, 2752523 /* regdef-ec:GPR64common */, def early-clobber %1, !0
29+
; CHECK-NEXT: INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef-ec:GPR64common */, def early-clobber %0, {{[0-9]+}} /* regdef-ec:GPR64common */, def early-clobber %1, !0
3030
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY %0
3131
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY %1
3232
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]]
@@ -54,7 +54,7 @@ entry:
5454
define i32 @test_single_register_output() nounwind ssp {
5555
; CHECK-LABEL: name: test_single_register_output
5656
; CHECK: bb.1.entry:
57-
; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %0
57+
; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0
5858
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %0
5959
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
6060
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -66,7 +66,7 @@ entry:
6666
define i64 @test_single_register_output_s64() nounwind ssp {
6767
; CHECK-LABEL: name: test_single_register_output_s64
6868
; CHECK: bb.1.entry:
69-
; CHECK-NEXT: INLINEASM &"mov $0, 7", 0 /* attdialect */, 2752522 /* regdef:GPR64common */, def %0
69+
; CHECK-NEXT: INLINEASM &"mov $0, 7", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR64common */, def %0
7070
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY %0
7171
; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
7272
; CHECK-NEXT: RET_ReallyLR implicit $x0
@@ -79,7 +79,7 @@ entry:
7979
define float @test_multiple_register_outputs_same() #0 {
8080
; CHECK-LABEL: name: test_multiple_register_outputs_same
8181
; CHECK: bb.1 (%ir-block.0):
82-
; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %0, 1703946 /* regdef:GPR32common */, def %1
82+
; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:GPR32common */, def %1
8383
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %0
8484
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
8585
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
@@ -96,7 +96,7 @@ define float @test_multiple_register_outputs_same() #0 {
9696
define double @test_multiple_register_outputs_mixed() #0 {
9797
; CHECK-LABEL: name: test_multiple_register_outputs_mixed
9898
; CHECK: bb.1 (%ir-block.0):
99-
; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %0, 2555914 /* regdef:FPR64 */, def %1
99+
; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:FPR64 */, def %1
100100
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %0
101101
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY %1
102102
; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)
@@ -125,7 +125,7 @@ define zeroext i8 @test_register_output_trunc(ptr %src) nounwind {
125125
; CHECK-NEXT: liveins: $x0
126126
; CHECK-NEXT: {{ $}}
127127
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
128-
; CHECK-NEXT: INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %1
128+
; CHECK-NEXT: INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1
129129
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
130130
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
131131
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
@@ -155,7 +155,7 @@ define void @test_input_register_imm() {
155155
; CHECK: bb.1 (%ir-block.0):
156156
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
157157
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY [[C]](s64)
158-
; CHECK-NEXT: INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, 2752521 /* reguse:GPR64common */, [[COPY]]
158+
; CHECK-NEXT: INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:GPR64common */, [[COPY]]
159159
; CHECK-NEXT: RET_ReallyLR
160160
call void asm sideeffect "mov x0, $0", "r"(i64 42)
161161
ret void
@@ -190,7 +190,7 @@ define zeroext i8 @test_input_register(ptr %src) nounwind {
190190
; CHECK-NEXT: {{ $}}
191191
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
192192
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]](p0)
193-
; CHECK-NEXT: INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %1, 2752521 /* reguse:GPR64common */, [[COPY1]]
193+
; CHECK-NEXT: INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1, {{[0-9]+}} /* reguse:GPR64common */, [[COPY1]]
194194
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %1
195195
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
196196
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
@@ -207,7 +207,7 @@ define i32 @test_memory_constraint(ptr %a) nounwind {
207207
; CHECK-NEXT: liveins: $x0
208208
; CHECK-NEXT: {{ $}}
209209
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
210-
; CHECK-NEXT: INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, 1703946 /* regdef:GPR32common */, def %1, 262158 /* mem:m */, [[COPY]](p0)
210+
; CHECK-NEXT: INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1, 262158 /* mem:m */, [[COPY]](p0)
211211
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %1
212212
; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
213213
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -221,7 +221,7 @@ define i16 @test_anyext_input() {
221221
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
222222
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
223223
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
224-
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1703946 /* regdef:GPR32common */, def %0, 1703945 /* reguse:GPR32common */, [[COPY]]
224+
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* reguse:GPR32common */, [[COPY]]
225225
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %0
226226
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
227227
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
@@ -237,7 +237,7 @@ define i16 @test_anyext_input_with_matching_constraint() {
237237
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
238238
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
239239
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
240-
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1703946 /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
240+
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)
241241
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %0
242242
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
243243
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)

‎llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,7 @@ define void @test2() #0 personality ptr @__gcc_personality_v0 {
7171
; CHECK-NEXT: G_INVOKE_REGION_START
7272
; CHECK-NEXT: EH_LABEL <mcsymbol >
7373
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY [[DEF]](p0)
74-
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2752521 /* reguse:GPR64common */, [[COPY]]
74+
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:GPR64common */, [[COPY]]
7575
; CHECK-NEXT: EH_LABEL <mcsymbol >
7676
; CHECK-NEXT: G_BR %bb.2
7777
; CHECK-NEXT: {{ $}}

‎llvm/test/CodeGen/AArch64/aarch64-sme2-asm.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ entry:
55
; CHECK: %0:ppr = COPY $p0
66
; CHECK: STR_PXI %0, %stack.0.predcnt.addr, 0 :: (store unknown-size into %ir.predcnt.addr, align 2)
77
; CHECK: %1:pnr_p8to15 = COPY %0
8-
; CHECK: INLINEASM &"ld1w {z0.s,z1.s,z2.s,z3.s}, $0/z, [x10]", 1 /* sideeffect attdialect */, 458761 /* reguse:PNR_p8to15 */, %1
8+
; CHECK: INLINEASM &"ld1w {z0.s,z1.s,z2.s,z3.s}, $0/z, [x10]", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:PNR_p8to15 */, %1
99
; CHECK: RET_ReallyLR
1010
%predcnt.addr = alloca target("aarch64.svcount"), align 2
1111
store target("aarch64.svcount") %predcnt, ptr %predcnt.addr, align 2
@@ -19,7 +19,7 @@ entry:
1919
; CHECK: %0:ppr = COPY $p0
2020
; CHECK: STR_PXI %0, %stack.0.predcnt.addr, 0 :: (store unknown-size into %ir.predcnt.addr, align 2)
2121
; CHECK: %1:pnr = COPY %0
22-
; CHECK: INLINEASM &"ld1w {z0.s,z1.s,z2.s,z3.s}, $0/z, [x10]", 1 /* sideeffect attdialect */, 262153 /* reguse:PNR */, %1
22+
; CHECK: INLINEASM &"ld1w {z0.s,z1.s,z2.s,z3.s}, $0/z, [x10]", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:PNR */, %1
2323
; CHECK: RET_ReallyLR
2424
%predcnt.addr = alloca target("aarch64.svcount"), align 2
2525
store target("aarch64.svcount") %predcnt, ptr %predcnt.addr, align 2
@@ -33,7 +33,7 @@ entry:
3333
; CHECK: %0:ppr = COPY $p0
3434
; CHECK: STR_PXI %0, %stack.0.predcnt.addr, 0 :: (store unknown-size into %ir.predcnt.addr, align 2)
3535
; CHECK: %1:pnr_3b = COPY %0
36-
; CHECK: INLINEASM &"fadd z0.h, $0/m, z0.h, #0.5", 1 /* sideeffect attdialect */, 393225 /* reguse:PNR_3b */, %1
36+
; CHECK: INLINEASM &"fadd z0.h, $0/m, z0.h, #0.5", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:PNR_3b */, %1
3737
; CHECK: RET_ReallyLR
3838
%predcnt.addr = alloca target("aarch64.svcount"), align 2
3939
store target("aarch64.svcount") %predcnt, ptr %predcnt.addr, align 2

‎llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ define i32 @test0() {
1818
; CHECK: bb.0.entry:
1919
; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
2020
; CHECK-NEXT: {{ $}}
21-
; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %5, 13 /* imm */, %bb.1
21+
; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %5, 13 /* imm */, %bb.1
2222
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %5
2323
; CHECK-NEXT: B %bb.2
2424
; CHECK-NEXT: {{ $}}
@@ -31,7 +31,7 @@ define i32 @test0() {
3131
; CHECK-NEXT: bb.2.direct:
3232
; CHECK-NEXT: successors: %bb.4(0x80000000), %bb.3(0x00000000)
3333
; CHECK-NEXT: {{ $}}
34-
; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %7, 13 /* imm */, %bb.3
34+
; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %7, 13 /* imm */, %bb.3
3535
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY %7
3636
; CHECK-NEXT: B %bb.4
3737
; CHECK-NEXT: {{ $}}
@@ -107,7 +107,7 @@ define i32 @dont_split1() {
107107
; CHECK: bb.0.entry:
108108
; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)
109109
; CHECK-NEXT: {{ $}}
110-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %1, 13 /* imm */, %bb.2
110+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1, 13 /* imm */, %bb.2
111111
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %1
112112
; CHECK-NEXT: B %bb.1
113113
; CHECK-NEXT: {{ $}}
@@ -168,7 +168,7 @@ define i32 @dont_split3() {
168168
; CHECK: bb.0.entry:
169169
; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)
170170
; CHECK-NEXT: {{ $}}
171-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %0, 13 /* imm */, %bb.2
171+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, 13 /* imm */, %bb.2
172172
; CHECK-NEXT: B %bb.1
173173
; CHECK-NEXT: {{ $}}
174174
; CHECK-NEXT: bb.1.x:
@@ -194,7 +194,7 @@ define i32 @split_me0() {
194194
; CHECK: bb.0.entry:
195195
; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
196196
; CHECK-NEXT: {{ $}}
197-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
197+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
198198
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3
199199
; CHECK-NEXT: B %bb.2
200200
; CHECK-NEXT: {{ $}}
@@ -244,7 +244,7 @@ define i32 @split_me1(i1 %z) {
244244
; CHECK-NEXT: bb.1.w:
245245
; CHECK-NEXT: successors: %bb.3(0x80000000), %bb.2(0x00000000)
246246
; CHECK-NEXT: {{ $}}
247-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %5, 13 /* imm */, %bb.2, 13 /* imm */, %bb.2
247+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %5, 13 /* imm */, %bb.2, 13 /* imm */, %bb.2
248248
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY %5
249249
; CHECK-NEXT: B %bb.3
250250
; CHECK-NEXT: {{ $}}
@@ -297,7 +297,7 @@ define i32 @split_me2(i1 %z) {
297297
; CHECK-NEXT: bb.1.w:
298298
; CHECK-NEXT: successors: %bb.3(0x80000000), %bb.2(0x00000000)
299299
; CHECK-NEXT: {{ $}}
300-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %6, 13 /* imm */, %bb.2, 13 /* imm */, %bb.2
300+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %6, 13 /* imm */, %bb.2, 13 /* imm */, %bb.2
301301
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY %6
302302
; CHECK-NEXT: B %bb.3
303303
; CHECK-NEXT: {{ $}}
@@ -340,7 +340,7 @@ define i32 @dont_split4() {
340340
; CHECK: bb.0.entry:
341341
; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)
342342
; CHECK-NEXT: {{ $}}
343-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.2
343+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.2
344344
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3
345345
; CHECK-NEXT: B %bb.1
346346
; CHECK-NEXT: {{ $}}
@@ -379,7 +379,7 @@ define i32 @dont_split5() {
379379
; CHECK: bb.0.entry:
380380
; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
381381
; CHECK-NEXT: {{ $}}
382-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
382+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
383383
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3
384384
; CHECK-NEXT: B %bb.2
385385
; CHECK-NEXT: {{ $}}
@@ -410,7 +410,7 @@ define i32 @split_me3() {
410410
; CHECK: bb.0.entry:
411411
; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
412412
; CHECK-NEXT: {{ $}}
413-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
413+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
414414
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3
415415
; CHECK-NEXT: B %bb.2
416416
; CHECK-NEXT: {{ $}}
@@ -456,7 +456,7 @@ define i32 @dont_split6(i32 %0) {
456456
; CHECK-NEXT: {{ $}}
457457
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %2, %bb.2
458458
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32common = COPY [[PHI]]
459-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %4, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3), 13 /* imm */, %bb.2
459+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %4, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3), 13 /* imm */, %bb.2
460460
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY %4
461461
; CHECK-NEXT: B %bb.3
462462
; CHECK-NEXT: {{ $}}
@@ -491,7 +491,7 @@ define i32 @split_me4() {
491491
; CHECK: bb.0.entry:
492492
; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
493493
; CHECK-NEXT: {{ $}}
494-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
494+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
495495
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3
496496
; CHECK-NEXT: B %bb.2
497497
; CHECK-NEXT: {{ $}}
@@ -522,7 +522,7 @@ define i32 @split_me5() {
522522
; CHECK: bb.0.entry:
523523
; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
524524
; CHECK-NEXT: {{ $}}
525-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 1703946 /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
525+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %3, 13 /* imm */, %bb.1
526526
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %3
527527
; CHECK-NEXT: B %bb.2
528528
; CHECK-NEXT: {{ $}}

‎llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -91,10 +91,10 @@ body: |
9191
; CHECK-NEXT: {{ $}}
9292
; CHECK-NEXT: [[LOADgot:%[0-9]+]]:gpr64common = LOADgot target-flags(aarch64-got) @c
9393
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
94-
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
94+
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
9595
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY %2
9696
; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
97-
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
97+
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
9898
; CHECK-NEXT: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr %2
9999
; CHECK-NEXT: nofpexcept FCMPDrr %4, killed [[FNEGDr]], implicit-def $nzcv, implicit $fpcr
100100
; CHECK-NEXT: Bcc 1, %bb.2, implicit $nzcv

‎llvm/test/CodeGen/AArch64/peephole-insvigpr.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -487,7 +487,7 @@ body: |
487487
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
488488
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
489489
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[DEF]]
490-
; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 2359306 /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
490+
; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, {{[0-9]+}} /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
491491
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
492492
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
493493
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF

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