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[mlir] GEMM Hopper Tensor Core Integration Test
This test aims to validate the correctness of the supported GEMM kernels in NVGPU dialects, with current support for Multistage and Warp Specialization kernels. The test constructs and metaprograms IR using Python bindings, allowing generic IR building. This flexibility enables changes to the shape, tile size, or data type of the GEMM for testing purposes. The entry function is `matmul`, where one can specify GEMM shape, tile size, data type, GEMM algorithm (Multistage or Warp Specialization), and the maximum number of stages. Verification is done via numpy's matmul operation. Example: ``` matmul(input_type=np.float16, # input types output_type=np.float32, # output type M=4096, N=4096, K=4096, # Shape BLOCK_M=128, BLOCK_N=128, BLOCK_K=64, # Tile Size use_warp_specialization=True, # Enable Warp Specialization max_num_stages=3) # Number of stages in shared memory ``` ### Parallelism Across CTAs GEMM includes three loops defining the shape of the GEMM, specified in the `matmul` function. The program builds IR using the following loop structure, tiling the loops with the given tile size and parallelizing the two outermost loops into the first and second dimensions of CTAs. ``` for(bi = 0; i < M; i += BLOCK_M) # parallelize across blockIdx.x for(bj = 0; j < N; j += BLOCK_N) # parallelize across blockIdx.y for(bk = 0; k < K; K += BLOCK_K) for(i = bi; i < (bi + BLOCK_M); ++i) for(j = bj; j < (bj + BLOCK_N); ++j) for(k = bk; k < (bk + BLOCK_K); ++k) ``` ## Multistage Kernel This kernel launches a single warp group (128 threads). The primary thread (pthread) requests load from TMA. Threads collectively wait for the data and perform mma operations. After completing the shape, threads together store first fragmented registers to shared memory, then from shared memory to global memory; this part is called the epilogue. Execution Timeline of Multistage Kernel with 3 stages: ``` +-------+----------------+--------------------+--------------------+--------------------+-----+-----------------------+ | |Prologue ----> |MainLoop ----> |Epilogue | +-------+----------------+--------------------+--------------------+--------------------+-----+-----------------------+ |pthread|[tma-0,1,2] |[wait-0][mma][tma-2]|[wait-1][mma][tma-0]|[wait-2][mma][tma-1]| ... | [mma-wait] |[epilogue]| |wgroup | ........ |[wait-0][mma] |[wait-1][mma] |[wait-2][mma] | ... | [mma-wait] |[epilogue]| +-------+----------------+--------------------+--------------------+--------------------+-----+-----------------------+ ``` ## Warp Specialization Kernel This kernel launches 2 warp groups (2x128 threads) per CTA, specializing one as `producer warp group` and another as `consumer warp group`. The `producer warp group` is responsible for requesting TMA load, while the `consumer warp group` performs the mma operation. The epilogue section is handled by the `consumer warp group` as its threads own the fragmented registers. Execution Timeline of Warp Specialization Kernel with 2 stages: ``` +--------+--------+---------+---------+---------+-----------------------+---+--------------+-----------------+ | |MainLoop ----> | 1st Epilogue | 2nd Epilogue | +--------+--------+---------+---------+---------+-----------------------+---+--------------+-----------------+ |pthread1|[tma-0] | [tma-1] | [tma-0] | [tma-1] | ..........................| ........... | [shmem->global] | |wgroup1 | .......| | | | | | [shmem->global] | +--------+--------+---------+---------+---------+-----------------------+---+--------------+-----------------+ |wgroup2 |[wait-0][mma], [wait-1][mma], [wait-0][mma], [wait-1][mma], ......| [reg->shmem] | [shmem->global]| +--------+--------+---------+---------+---------+-----------------------+---+--------------+-----------------+ ```
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‎mlir/test/Integration/GPU/CUDA/sm90/python/lit.local.cfg

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if not config.enable_cuda_runner or not config.mlir_run_cuda_sm90_tests:
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config.unsupported = True

‎mlir/test/Integration/GPU/CUDA/sm90/python/matmul.py

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# RUN: env SUPPORT_LIB=%mlir_cuda_runtime \
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# RUN: %PYTHON %s | FileCheck %s
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# CHECK: PASS
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# ===--- GEMM Hopper Tensor Core Integration Test ---===
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#
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# This test aims to validate the correctness of the supported GEMM kernels in
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# NVGPU dialects, with current support for Multistage and Warp Specialization
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# kernels.
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# The test constructs and metaprograms IR using Python bindings, allowing
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# generic IR building. This flexibility enables changes to the shape,
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# tile size, or data type of the GEMM for testing purposes.
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# The entry function is `matmul`, where one can specify GEMM shape, tile size,
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# data type, GEMM algorithm (Multistage or Warp Specialization), and the maximum
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# number of stages.
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# Verification is done via numpy's matmul operation.
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#
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# Example:
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# matmul(input_type=np.float16, # input types
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# output_type=np.float32, # output type
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# M=4096, N=4096, K=4096, # Shape
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# BLOCK_M=128, BLOCK_N=128, BLOCK_K=64, # Tile Size
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# use_warp_specialization=True, # Enable Warp Specialization
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# max_num_stages=3) # Number of stages in shared memory
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#
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# ===--- Parallelism Across CTAs ---===
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#
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# GEMM includes three loops defining the shape of the GEMM, specified in the
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# `matmul` function.
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# The program builds IR using the following loop structure, tiling the loops
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# with the given tile size and parallelizing the two outermost loops into the
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# first and second dimensions of CTAs.
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#
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# for(bi = 0; i < M; i += BLOCK_M) # parallelize across blockIdx.x
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# for(bj = 0; j < N; j += BLOCK_N) # parallelize across blockIdx.y
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# for(bk = 0; k < K; K += BLOCK_K)
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# for(i = bi; i < (bi + BLOCK_M); ++i)
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# for(j = bj; j < (bj + BLOCK_N); ++j)
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# for(k = bk; k < (bk + BLOCK_K); ++k)
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#
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# ===--- Multistage Kernel ---===
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#
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# This kernel launches a single warp group (128 threads). The primary thread
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# (pthread) requests load from TMA. Threads collectively wait for the data and
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# perform mma operations. After completing the shape, threads together store
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# first fragmented registers to shared memory, then from shared memory to global
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# memory; this part is called the epilogue.
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#
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# Execution Timeline of Multistage Kernel with 3 stages:
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# +-------+----------------+--------------------+--------------------+--------------------+-----+-----------------------+
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# | |Prologue ----> |MainLoop ----> |Epilogue |
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# +-------+----------------+--------------------+--------------------+--------------------+-----+-----------------------+
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# |pthread|[tma-0,1,2] |[wait-0][mma][tma-2]|[wait-1][mma][tma-0]|[wait-2][mma][tma-1]| ... | [mma-wait] |[epilogue]|
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# |wgroup | ........ |[wait-0][mma] |[wait-1][mma] |[wait-2][mma] | ... | [mma-wait] |[epilogue]|
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# +-------+----------------+--------------------+--------------------+--------------------+-----+-----------------------+
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#
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# ===--- Warp Specialization Kernel ---===
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#
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# This kernel launches 2 warp groups (2x128 threads) per CTA, specializing one
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# as `producer warp group` and another as `consumer warp group`. The
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# `producer warp group` is responsible for requesting TMA load, while the
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# `consumer warp group` performs the mma operation. The epilogue section is
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# handled by the `consumer warp group` as its threads own the fragmented registers.
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#
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# Execution Timeline of Warp Specialization Kernel with 2 stages:
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# +--------+--------+---------+---------+---------+-----------------------+---+--------------+-----------------+
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# | |MainLoop ----> | 1st Epilogue | 2nd Epilogue |
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# +--------+--------+---------+---------+---------+-----------------------+---+--------------+-----------------+
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# |pthread1|[tma-0] | [tma-1] | [tma-0] | [tma-1] | ..........................| ........... | [shmem->global] |
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# |wgroup1 | .......| | | | | | [shmem->global] |
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# +--------+--------+---------+---------+---------+-----------------------+---+--------------+-----------------+
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# |wgroup2 |[wait-0][mma], [wait-1][mma], [wait-0][mma], [wait-1][mma], ......| [reg->shmem] | [shmem->global]|
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# +--------+--------+---------+---------+---------+-----------------------+---+--------------+-----------------+
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import errno
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import numpy as np
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import subprocess
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import ctypes
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from tools import nvgpucompiler
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from tools import matmulBuilder
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import contextlib
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import os
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import sys
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import pathlib
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import ctypes
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from mlir import runtime as rt
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def generate_matmul(input_type=np.float16,
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output_type=np.float32,
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M=4096,
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N=4096,
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K=4096,
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BLOCK_M=128,
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BLOCK_N=128,
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BLOCK_K=64,
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use_warp_specilization=True,
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saveIR=False,
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max_num_stages=3):
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with matmulBuilder.ir.Context() as ctx, matmulBuilder.ir.Location.unknown():
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if use_warp_specilization:
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mlir_nvgpu_module = matmulBuilder.generate_matmul_ws(input_type, output_type, M, N, K, BLOCK_M, BLOCK_N,
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BLOCK_K, max_num_stages)
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else:
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mlir_nvgpu_module = matmulBuilder.generate_matmul_multistage(input_type, output_type, M, N, K, BLOCK_M,
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BLOCK_N, BLOCK_K, max_num_stages)
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mlir_nvgpu_module.operation.verify()
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# Save generated IR
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if saveIR:
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# print(mlir_nvgpu_module)
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original_stdout = sys.stdout
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with open('gemm.mlir', 'w') as f:
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sys.stdout = f
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print(mlir_nvgpu_module)
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sys.stdout = original_stdout
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# Get compiler
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options = f"cubin-chip=sm_90a cubin-features=+ptx80 opt-level=3"
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support_lib = os.getenv("SUPPORT_LIB")
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if not os.path.exists(support_lib):
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raise FileNotFoundError(errno.ENOENT, os.strerror(errno.ENOENT), support_lib)
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compiler = nvgpucompiler.NvgpuCompiler(options, opt_level=3, shared_libs=[support_lib])
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# Compile
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engine = compiler.compile_and_jit(mlir_nvgpu_module)
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return engine
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def matmul(input_type=np.float16,
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output_type=np.float32,
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M=128,
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N=128,
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K=128,
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BLOCK_M=128,
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BLOCK_N=128,
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BLOCK_K=64,
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use_warp_specilization=True,
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saveIR=False,
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max_num_stages=3,
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print_results=False,
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no_verify=False):
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# Print the configuration
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ity = "f16" if input_type == np.float16 else "f32"
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oty = "f16" if output_type == np.float16 else "f32"
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gemmty = "Warp Specilization" if use_warp_specilization else "Multistage"
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print("===-- Running GEMM " + gemmty + " " + oty + " += " + ity + " * " + ity + ", Size " + str(M) + "x" + str(N) +
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"x" + str(K) + ", Tile " + str(BLOCK_M) + "x" + str(BLOCK_N) + "x" + str(BLOCK_K) + ", stages " +
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str(max_num_stages) + " --===")
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# Build IR and compile
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engine = generate_matmul(input_type, output_type, M, N, K, BLOCK_M, BLOCK_N, BLOCK_K, use_warp_specilization,
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saveIR, max_num_stages)
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# Allocate matrices and invoke the matmul
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c = np.zeros((M, N), output_type)
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a = np.random.randn(M, K).astype(input_type)
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b = np.random.randn(K, N).astype(input_type)
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mem_a = ctypes.pointer(ctypes.pointer(rt.get_ranked_memref_descriptor(a)))
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mem_b = ctypes.pointer(ctypes.pointer(rt.get_ranked_memref_descriptor(b)))
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mem_c = ctypes.pointer(ctypes.pointer(rt.get_ranked_memref_descriptor(c)))
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kernelName = "mlir_matmul_warpspecialized" if use_warp_specilization else "mlir_matmul_multistage"
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# Launch the MLIR generated kernel
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engine.invoke(kernelName, mem_a, mem_b, mem_c)
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float_formatter = "{:.2f}".format
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np.set_printoptions(formatter={'float_kind': float_formatter})
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if print_results:
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print(c)
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# Verify the results
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if not no_verify:
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ref = a.astype(input_type) @ b.astype(input_type)
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if print_results:
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print(ref)
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np.testing.assert_allclose(c, ref, rtol=5e-03, atol=1e-01)
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print("PASS ")
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# GEMM Multistage f32 += f16 * f16
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matmul(np.float16, np.float32, 128, 128, 4096, max_num_stages=3, use_warp_specilization=False)
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# GEMM Warp Specilized f32 += f16 * f16
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matmul(np.float16, np.float32, 256, 1024, 512, max_num_stages=3, use_warp_specilization=True)

‎mlir/test/Integration/GPU/CUDA/sm90/python/tools/lit.local.cfg

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# Files in this directory are tools, not tests.
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config.unsupported = True
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