[CodeGen][AArch64] Enable LDAPR under +RCPC

This is a follow-up to D126250 and enables LDAPR
if the RCPC extensions are enabled.

Test plan: ninja check-all

Differential revision: https://reviews.llvm.org/D137590

Author: alexander-shaposhnikov

llvm/lib/Target/AArch64/AArch64.td

@@ -70,10 +70,6 @@ def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
 def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true",
   "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">;
 
-def FeatureLDAPR : SubtargetFeature<"ldapr", "HasLDAPR", "true",
-  "Use LDAPR to lower atomic loads; experimental until we "
-  "have more testing/a formal correctness proof">;
-
 def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
   "Enable out of line atomics to support LSE instructions">;
 

llvm/lib/Target/AArch64/AArch64InstrAtomics.td

@@ -49,8 +49,7 @@ class seq_cst_load<PatFrags base>
   let IsAtomicOrderingSequentiallyConsistent = 1;
 }
 
-// RCPC extension, currently opt-in under a separate feature.
-let Predicates = [HasLDAPR] in {
+let Predicates = [HasRCPC] in {
   // v8.3 Release Consistent Processor Consistent support, optional in v8.2.
   // 8-bit loads
   def : Pat<(acquiring_load<atomic_load_8> GPR64sp:$ptr), (LDAPRB GPR64sp:$ptr)>;

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -177,8 +177,6 @@ def HasNEONorSME
                 "neon or sme">;
 def HasRCPC          : Predicate<"Subtarget->hasRCPC()">,
                                  AssemblerPredicateWithAll<(all_of FeatureRCPC), "rcpc">;
-def HasLDAPR         : Predicate<"Subtarget->hasLDAPR()">,
-                                 AssemblerPredicateWithAll<(all_of FeatureLDAPR), "ldapr">;
 def HasAltNZCV       : Predicate<"Subtarget->hasAlternativeNZCV()">,
                        AssemblerPredicateWithAll<(all_of FeatureAltFPCmp), "altnzcv">;
 def HasFRInt3264     : Predicate<"Subtarget->hasFRInt3264()">,

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

@@ -2829,7 +2829,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
         static constexpr unsigned LDAROpcodes[] = {
             AArch64::LDARB, AArch64::LDARH, AArch64::LDARW, AArch64::LDARX};
         ArrayRef<unsigned> Opcodes =
-            STI.hasLDAPR() && Order != AtomicOrdering::SequentiallyConsistent
+            STI.hasRCPC() && Order != AtomicOrdering::SequentiallyConsistent
                 ? LDAPROpcodes
                 : LDAROpcodes;
         I.setDesc(TII.get(Opcodes[Log2_32(MemSizeInBytes)]));