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Precommit tests for new targets
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‎llvm/test/CodeGen/ARM/scmp.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=thumbv7-apple-darwin %s -o - | FileCheck %s
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define i8 @scmp_8_8(i8 %x, i8 %y) nounwind {
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; CHECK-LABEL: scmp_8_8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: sxtb r2, r0
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: sxtb r1, r1
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: it gt
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; CHECK-NEXT: movgt r0, #1
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne r0, #1
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt.w r0, #-1
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.scmp(i8 %x, i8 %y)
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ret i8 %1
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}
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define i8 @scmp_8_16(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: scmp_8_16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: sxth r2, r0
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: sxth r1, r1
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: it gt
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; CHECK-NEXT: movgt r0, #1
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne r0, #1
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt.w r0, #-1
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.scmp(i16 %x, i16 %y)
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ret i8 %1
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}
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define i8 @scmp_8_32(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: scmp_8_32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: movs r2, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: it gt
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; CHECK-NEXT: movgt r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne r2, #1
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt.w r2, #-1
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.scmp(i32 %x, i32 %y)
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ret i8 %1
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}
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define i8 @scmp_8_64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: scmp_8_64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: subs.w r12, r2, r0
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; CHECK-NEXT: mov.w r9, #0
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; CHECK-NEXT: sbcs.w r12, r3, r1
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt.w r9, #1
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; CHECK-NEXT: cmp.w r9, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne.w r9, #1
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; CHECK-NEXT: subs r0, r0, r2
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; CHECK-NEXT: sbcs.w r0, r1, r3
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt.w r9, #-1
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; CHECK-NEXT: mov r0, r9
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.scmp(i64 %x, i64 %y)
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ret i8 %1
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}
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define i8 @scmp_8_128(i128 %x, i128 %y) nounwind {
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; CHECK-LABEL: scmp_8_128:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: push {r4, r5, r6, lr}
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; CHECK-NEXT: ldrd r12, lr, [sp, #16]
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; CHECK-NEXT: mov.w r9, #0
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; CHECK-NEXT: ldrd r4, r5, [sp, #24]
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; CHECK-NEXT: subs.w r6, r12, r0
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; CHECK-NEXT: sbcs.w r6, lr, r1
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; CHECK-NEXT: sbcs.w r6, r4, r2
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; CHECK-NEXT: sbcs.w r6, r5, r3
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt.w r9, #1
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; CHECK-NEXT: cmp.w r9, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne.w r9, #1
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; CHECK-NEXT: subs.w r0, r0, r12
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; CHECK-NEXT: sbcs.w r0, r1, lr
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; CHECK-NEXT: sbcs.w r0, r2, r4
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; CHECK-NEXT: sbcs.w r0, r3, r5
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt.w r9, #-1
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; CHECK-NEXT: mov r0, r9
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; CHECK-NEXT: pop {r4, r5, r6, pc}
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%1 = call i8 @llvm.scmp(i128 %x, i128 %y)
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ret i8 %1
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}
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define i32 @scmp_32_32(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: scmp_32_32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: movs r2, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: it gt
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; CHECK-NEXT: movgt r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne r2, #1
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt.w r2, #-1
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%1 = call i32 @llvm.scmp(i32 %x, i32 %y)
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ret i32 %1
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}
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define i32 @scmp_32_64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: scmp_32_64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: subs.w r12, r2, r0
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; CHECK-NEXT: mov.w r9, #0
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; CHECK-NEXT: sbcs.w r12, r3, r1
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt.w r9, #1
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; CHECK-NEXT: cmp.w r9, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne.w r9, #1
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; CHECK-NEXT: subs r0, r0, r2
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; CHECK-NEXT: sbcs.w r0, r1, r3
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt.w r9, #-1
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; CHECK-NEXT: mov r0, r9
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; CHECK-NEXT: bx lr
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%1 = call i32 @llvm.scmp(i64 %x, i64 %y)
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ret i32 %1
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}
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define i64 @scmp_64_64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: scmp_64_64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: subs.w r12, r0, r2
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; CHECK-NEXT: mov.w r9, #0
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; CHECK-NEXT: sbcs.w r12, r1, r3
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt.w r12, #1
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; CHECK-NEXT: subs r0, r2, r0
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; CHECK-NEXT: sbcs.w r0, r3, r1
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt.w r9, #1
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; CHECK-NEXT: cmp.w r9, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne.w r9, #1
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; CHECK-NEXT: cmp.w r12, #0
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; CHECK-NEXT: itt ne
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; CHECK-NEXT: movne.w r9, #-1
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; CHECK-NEXT: movne.w r12, #-1
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; CHECK-NEXT: mov r0, r9
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; CHECK-NEXT: mov r1, r12
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; CHECK-NEXT: bx lr
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%1 = call i64 @llvm.scmp(i64 %x, i64 %y)
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ret i64 %1
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}

‎llvm/test/CodeGen/ARM/ucmp.ll

Lines changed: 177 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=thumbv7-apple-darwin %s -o - | FileCheck %s
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define i8 @ucmp_8_8(i8 %x, i8 %y) nounwind {
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; CHECK-LABEL: ucmp_8_8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb r2, r0
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: uxtb r1, r1
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: it hi
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; CHECK-NEXT: movhi r0, #1
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne r0, #1
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo.w r0, #-1
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.ucmp(i8 %x, i8 %y)
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ret i8 %1
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}
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define i8 @ucmp_8_16(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: ucmp_8_16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxth r2, r0
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: uxth r1, r1
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: it hi
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; CHECK-NEXT: movhi r0, #1
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne r0, #1
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo.w r0, #-1
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.ucmp(i16 %x, i16 %y)
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ret i8 %1
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}
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define i8 @ucmp_8_32(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: ucmp_8_32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: movs r2, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: it hi
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; CHECK-NEXT: movhi r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne r2, #1
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo.w r2, #-1
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
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ret i8 %1
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}
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define i8 @ucmp_8_64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: ucmp_8_64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: subs.w r12, r2, r0
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; CHECK-NEXT: mov.w r9, #0
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; CHECK-NEXT: sbcs.w r12, r3, r1
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo.w r9, #1
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; CHECK-NEXT: cmp.w r9, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne.w r9, #1
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; CHECK-NEXT: subs r0, r0, r2
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; CHECK-NEXT: sbcs.w r0, r1, r3
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo.w r9, #-1
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; CHECK-NEXT: mov r0, r9
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.ucmp(i64 %x, i64 %y)
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ret i8 %1
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}
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define i8 @ucmp_8_128(i128 %x, i128 %y) nounwind {
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; CHECK-LABEL: ucmp_8_128:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: push {r4, r5, r6, lr}
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; CHECK-NEXT: ldrd r12, lr, [sp, #16]
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; CHECK-NEXT: mov.w r9, #0
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; CHECK-NEXT: ldrd r4, r5, [sp, #24]
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; CHECK-NEXT: subs.w r6, r12, r0
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; CHECK-NEXT: sbcs.w r6, lr, r1
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; CHECK-NEXT: sbcs.w r6, r4, r2
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; CHECK-NEXT: sbcs.w r6, r5, r3
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo.w r9, #1
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; CHECK-NEXT: cmp.w r9, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne.w r9, #1
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; CHECK-NEXT: subs.w r0, r0, r12
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; CHECK-NEXT: sbcs.w r0, r1, lr
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; CHECK-NEXT: sbcs.w r0, r2, r4
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; CHECK-NEXT: sbcs.w r0, r3, r5
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo.w r9, #-1
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; CHECK-NEXT: mov r0, r9
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; CHECK-NEXT: pop {r4, r5, r6, pc}
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%1 = call i8 @llvm.ucmp(i128 %x, i128 %y)
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ret i8 %1
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}
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define i32 @ucmp_32_32(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: ucmp_32_32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: movs r2, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: it hi
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; CHECK-NEXT: movhi r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne r2, #1
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo.w r2, #-1
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
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ret i32 %1
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}
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define i32 @ucmp_32_64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: ucmp_32_64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: subs.w r12, r2, r0
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; CHECK-NEXT: mov.w r9, #0
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; CHECK-NEXT: sbcs.w r12, r3, r1
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo.w r9, #1
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; CHECK-NEXT: cmp.w r9, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne.w r9, #1
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; CHECK-NEXT: subs r0, r0, r2
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; CHECK-NEXT: sbcs.w r0, r1, r3
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo.w r9, #-1
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; CHECK-NEXT: mov r0, r9
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; CHECK-NEXT: bx lr
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%1 = call i32 @llvm.ucmp(i64 %x, i64 %y)
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ret i32 %1
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}
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define i64 @ucmp_64_64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: ucmp_64_64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: subs.w r12, r0, r2
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; CHECK-NEXT: mov.w r9, #0
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; CHECK-NEXT: sbcs.w r12, r1, r3
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo.w r12, #1
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; CHECK-NEXT: subs r0, r2, r0
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; CHECK-NEXT: sbcs.w r0, r3, r1
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo.w r9, #1
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; CHECK-NEXT: cmp.w r9, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne.w r9, #1
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; CHECK-NEXT: cmp.w r12, #0
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; CHECK-NEXT: itt ne
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; CHECK-NEXT: movne.w r9, #-1
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; CHECK-NEXT: movne.w r12, #-1
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; CHECK-NEXT: mov r0, r9
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; CHECK-NEXT: mov r1, r12
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; CHECK-NEXT: bx lr
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%1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
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ret i64 %1
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}

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