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[AArch64] Add tests for saturated truncate
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‎llvm/test/CodeGen/AArch64/qmovn.ll

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@@ -125,6 +125,117 @@ entry:
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ret <2 x i32> %t
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}
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define <2 x i32> @vqmovni64_smaxmin_u(<2 x i64> %s0) {
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; CHECK-LABEL: vqmovni64_smaxmin_u:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
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; CHECK-NEXT: cmgt v2.2d, v1.2d, v0.2d
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; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: cmgt v1.2d, v0.2d, #0
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp slt <2 x i64> %s0, <i64 4294967295, i64 4294967295>
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%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
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%c2 = icmp sgt <2 x i64> %s1, zeroinitializer
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%s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> zeroinitializer
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%t = trunc <2 x i64> %s2 to <2 x i32>
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ret <2 x i32> %t
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}
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define <2 x i32> @vqmovni64_sminmax_u(<2 x i64> %s0) {
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; CHECK-LABEL: vqmovni64_sminmax_u:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmgt v1.2d, v0.2d, #0
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; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: cmgt v1.2d, v2.2d, v0.2d
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp sgt <2 x i64> %s0, zeroinitializer
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%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> zeroinitializer
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%c2 = icmp slt <2 x i64> %s1, <i64 4294967295, i64 4294967295>
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%s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 4294967295, i64 4294967295>
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%t = trunc <2 x i64> %s2 to <2 x i32>
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ret <2 x i32> %t
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}
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define <4 x i16> @vqmovni32_smaxmin_u(<4 x i32> %s0) {
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; CHECK-LABEL: vqmovni32_smaxmin_u:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
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; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: movi v1.2d, #0000000000000000
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; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp slt <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>
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%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
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%c2 = icmp sgt <4 x i32> %s1, zeroinitializer
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%s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> zeroinitializer
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%t = trunc <4 x i32> %s2 to <4 x i16>
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ret <4 x i16> %t
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}
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define <4 x i16> @vqmovni32_sminmax_u(<4 x i32> %s0) {
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; CHECK-LABEL: vqmovni32_sminmax_u:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v1.2d, #0000000000000000
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; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
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; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp sgt <4 x i32> %s0, zeroinitializer
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%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> zeroinitializer
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%c2 = icmp slt <4 x i32> %s1, <i32 65535, i32 65535, i32 65535, i32 65535>
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%s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
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%t = trunc <4 x i32> %s2 to <4 x i16>
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ret <4 x i16> %t
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}
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define <8 x i8> @vqmovni16_smaxmin_u(<8 x i16> %s0) {
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; CHECK-LABEL: vqmovni16_smaxmin_u:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v1.2d, #0xff00ff00ff00ff
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; CHECK-NEXT: movi v2.2d, #0000000000000000
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; CHECK-NEXT: smin v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: smax v0.8h, v0.8h, v2.8h
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; CHECK-NEXT: xtn v0.8b, v0.8h
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp slt <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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%c2 = icmp sgt <8 x i16> %s1, zeroinitializer
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%s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> zeroinitializer
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%t = trunc <8 x i16> %s2 to <8 x i8>
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ret <8 x i8> %t
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}
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define <8 x i8> @vqmovni16_sminmax_u(<8 x i16> %s0) {
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; CHECK-LABEL: vqmovni16_sminmax_u:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v1.2d, #0000000000000000
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; CHECK-NEXT: movi v2.2d, #0xff00ff00ff00ff
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; CHECK-NEXT: smax v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: smin v0.8h, v0.8h, v2.8h
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; CHECK-NEXT: xtn v0.8b, v0.8h
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp sgt <8 x i16> %s0, zeroinitializer
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%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> zeroinitializer
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%c2 = icmp slt <8 x i16> %s1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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%s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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%t = trunc <8 x i16> %s2 to <8 x i8>
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ret <8 x i8> %t
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}
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define <2 x i32> @vqmovni64_umaxmin(<2 x i64> %s0) {
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; CHECK-LABEL: vqmovni64_umaxmin:
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; CHECK: // %bb.0: // %entry
@@ -347,3 +458,61 @@ entry:
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%shuffle = shufflevector <2 x i32> %x, <2 x i32> %trunc, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %shuffle
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}
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; Test the (concat_vectors (X), (trunc(smin(smax(Y, 0), 2^n))))) pattern.
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define <16 x i8> @sminsmax_range_unsigned_i16_to_i8(<8 x i8> %x, <8 x i16> %y) {
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; CHECK-LABEL: sminsmax_range_unsigned_i16_to_i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v2.2d, #0000000000000000
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; CHECK-NEXT: movi v3.2d, #0xff00ff00ff00ff
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: smax v1.8h, v1.8h, v2.8h
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; CHECK-NEXT: smin v1.8h, v1.8h, v3.8h
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; CHECK-NEXT: xtn2 v0.16b, v1.8h
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; CHECK-NEXT: ret
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entry:
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%min = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %y, <8 x i16> zeroinitializer)
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%max = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %min, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)
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%trunc = trunc <8 x i16> %max to <8 x i8>
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%shuffle = shufflevector <8 x i8> %x, <8 x i8> %trunc, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %shuffle
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}
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define <8 x i16> @sminsmax_range_unsigned_i32_to_i16(<4 x i16> %x, <4 x i32> %y) {
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; CHECK-LABEL: sminsmax_range_unsigned_i32_to_i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v2.2d, #0000000000000000
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
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; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff
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; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
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; CHECK-NEXT: xtn2 v0.8h, v1.4s
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; CHECK-NEXT: ret
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entry:
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%smax = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %y, <4 x i32> zeroinitializer)
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%smin = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %smax, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
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%trunc = trunc <4 x i32> %smin to <4 x i16>
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%shuffle = shufflevector <4 x i16> %x, <4 x i16> %trunc, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %shuffle
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}
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define <4 x i32> @sminsmax_range_unsigned_i64_to_i32(<2 x i32> %x, <2 x i64> %y) {
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; CHECK-LABEL: sminsmax_range_unsigned_i64_to_i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmgt v2.2d, v1.2d, #0
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; CHECK-NEXT: movi v3.2d, #0x000000ffffffff
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
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; CHECK-NEXT: cmgt v2.2d, v3.2d, v1.2d
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; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
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; CHECK-NEXT: orn v1.16b, v1.16b, v2.16b
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; CHECK-NEXT: xtn2 v0.4s, v1.2d
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; CHECK-NEXT: ret
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entry:
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%smax = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %y, <2 x i64> zeroinitializer)
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%smin = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %smax, <2 x i64> <i64 4294967295, i64 4294967295>)
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%trunc = trunc <2 x i64> %smin to <2 x i32>
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%shuffle = shufflevector <2 x i32> %x, <2 x i32> %trunc, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %shuffle
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}

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