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[RISCV] Use listconcat to shorten some of the profile feature lists. (#102356)
The profiles in a family gain more features overtime so each year can mostly inherit from the previous year. I did make an exception for Za128rs becoming Za64rs in RVA22. Technically Za64rs is a stricter requirement than Za128rs so it would be ok to have both, but I didn't want to change existing ISA strings. I used RVA20U64BaseFeatures as the base for RVB23U64 to shorten its list a bit. RVB23 is the first year for that family and was created as a reaction to too many features being added to RVA so inheriting from an earlier RVA seemed somewhat reasonable to me.
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‎llvm/lib/Target/RISCV/RISCVProfiles.td

Lines changed: 113 additions & 151 deletions
Original file line numberDiff line numberDiff line change
@@ -6,169 +6,113 @@
66
//
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//===----------------------------------------------------------------------===//
88

9-
class RISCVProfile<string name, list<SubtargetFeature> features>
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: SubtargetFeature<name, "Is" # NAME, "true",
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"RISC-V " # name # " profile", features> {
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// Indicates if the profile is not yet ratified, so should be treated as
13-
// experimental.
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bit Experimental = false;
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}
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class RISCVExperimentalProfile<string name, list<SubtargetFeature> features>
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: RISCVProfile<"experimental-"#name, features> {
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let Experimental = true;
19-
}
9+
//===----------------------------------------------------------------------===//
10+
// Profile Featuyre Lists
11+
//===----------------------------------------------------------------------===//
12+
13+
// RVI Profile Family
2014

2115
defvar RVI20U32Features = [Feature32Bit, FeatureStdExtI];
2216
defvar RVI20U64Features = [Feature64Bit, FeatureStdExtI];
2317

24-
defvar RVA20U64Features = [Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZicntr,
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FeatureStdExtZiccif,
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FeatureStdExtZiccrse,
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FeatureStdExtZiccamoa,
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FeatureStdExtZa128rs,
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FeatureStdExtZicclsm];
18+
// RVA Profile Family
19+
20+
defvar RVA20U64BaseFeatures = [Feature64Bit,
21+
FeatureStdExtI,
22+
FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
27+
FeatureStdExtZicntr,
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FeatureStdExtZiccif,
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FeatureStdExtZiccrse,
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FeatureStdExtZiccamoa,
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FeatureStdExtZicclsm];
32+
defvar RVA20U64Features = !listconcat(RVA20U64BaseFeatures,
33+
[FeatureStdExtZa128rs]);
3734

35+
defvar RVA20S64BaseFeatures = [FeatureStdExtZifencei,
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FeatureStdExtSvbare,
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FeatureStdExtSvade,
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FeatureStdExtSsccptr,
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FeatureStdExtSstvecd,
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FeatureStdExtSstvala];
3841
defvar RVA20S64Features = !listconcat(RVA20U64Features,
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[FeatureStdExtZifencei,
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FeatureStdExtSvbare,
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FeatureStdExtSvade,
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FeatureStdExtSsccptr,
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FeatureStdExtSstvecd,
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FeatureStdExtSstvala]);
42+
RVA20S64BaseFeatures);
4543

46-
defvar RVA22U64Features = [Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZicntr,
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FeatureStdExtZiccif,
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FeatureStdExtZiccrse,
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FeatureStdExtZiccamoa,
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FeatureStdExtZicclsm,
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FeatureStdExtZa64rs,
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FeatureStdExtZihpm,
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FeatureStdExtZihintpause,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbs,
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FeatureStdExtZic64b,
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FeatureStdExtZicbom,
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FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureStdExtZfhmin,
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FeatureStdExtZkt];
44+
defvar RVA22U64Features = !listconcat(RVA20U64BaseFeatures,
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[FeatureStdExtZa64rs,
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FeatureStdExtZihpm,
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FeatureStdExtZihintpause,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbs,
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FeatureStdExtZic64b,
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FeatureStdExtZicbom,
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FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureStdExtZfhmin,
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FeatureStdExtZkt]);
7057

58+
defvar RVA22S64BaseFeatures = !listconcat(RVA20S64BaseFeatures,
59+
[FeatureStdExtSscounterenw,
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FeatureStdExtSvpbmt,
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FeatureStdExtSvinval]);
7162
defvar RVA22S64Features = !listconcat(RVA22U64Features,
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[FeatureStdExtZifencei,
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FeatureStdExtSvbare,
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FeatureStdExtSvade,
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FeatureStdExtSsccptr,
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FeatureStdExtSstvecd,
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FeatureStdExtSstvala,
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FeatureStdExtSscounterenw,
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FeatureStdExtSvpbmt,
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FeatureStdExtSvinval]);
63+
RVA22S64BaseFeatures);
8164

82-
defvar RVA23U64Features = [Feature64Bit,
83-
FeatureStdExtI,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZicntr,
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FeatureStdExtZihpm,
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FeatureStdExtZiccif,
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FeatureStdExtZiccrse,
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FeatureStdExtZiccamoa,
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FeatureStdExtZicclsm,
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FeatureStdExtZa64rs,
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FeatureStdExtZihintpause,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbs,
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FeatureStdExtZic64b,
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FeatureStdExtZicbom,
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FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureStdExtZfhmin,
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FeatureStdExtZkt,
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FeatureStdExtV,
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FeatureStdExtZvfhmin,
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FeatureStdExtZvbb,
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FeatureStdExtZvkt,
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FeatureStdExtZihintntl,
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FeatureStdExtZicond,
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FeatureStdExtZimop,
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FeatureStdExtZcmop,
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FeatureStdExtZcb,
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FeatureStdExtZfa,
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FeatureStdExtZawrs];
65+
defvar RVA23U64Features = !listconcat(RVA22U64Features,
66+
[FeatureStdExtV,
67+
FeatureStdExtZvfhmin,
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FeatureStdExtZvbb,
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FeatureStdExtZvkt,
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FeatureStdExtZihintntl,
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FeatureStdExtZicond,
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FeatureStdExtZimop,
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FeatureStdExtZcmop,
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FeatureStdExtZcb,
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FeatureStdExtZfa,
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FeatureStdExtZawrs]);
11777

78+
defvar RVA23S64BaseFeatures = !listconcat(RVA22S64BaseFeatures,
79+
[FeatureStdExtSvnapot,
80+
FeatureStdExtSstc,
81+
FeatureStdExtSscofpmf,
82+
FeatureStdExtSsnpm,
83+
FeatureStdExtSsu64xl,
84+
FeatureStdExtH,
85+
FeatureStdExtSsstateen,
86+
FeatureStdExtShcounterenw,
87+
FeatureStdExtShvstvala,
88+
FeatureStdExtShtvala,
89+
FeatureStdExtShvstvecd,
90+
FeatureStdExtShvsatpa,
91+
FeatureStdExtShgatpa]);
11892
defvar RVA23S64Features = !listconcat(RVA23U64Features,
119-
[FeatureStdExtZifencei,
120-
FeatureStdExtSvbare,
121-
FeatureStdExtSvade,
122-
FeatureStdExtSsccptr,
123-
FeatureStdExtSstvecd,
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FeatureStdExtSstvala,
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FeatureStdExtSscounterenw,
126-
FeatureStdExtSvpbmt,
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FeatureStdExtSvinval,
128-
FeatureStdExtSvnapot,
129-
FeatureStdExtSstc,
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FeatureStdExtSscofpmf,
131-
FeatureStdExtSsnpm,
132-
FeatureStdExtSsu64xl,
133-
FeatureStdExtH,
134-
FeatureStdExtSsstateen,
135-
FeatureStdExtShcounterenw,
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FeatureStdExtShvstvala,
137-
FeatureStdExtShtvala,
138-
FeatureStdExtShvstvecd,
139-
FeatureStdExtShvsatpa,
140-
FeatureStdExtShgatpa]);
141-
142-
defvar RVB23U64Features = [Feature64Bit,
143-
FeatureStdExtI,
144-
FeatureStdExtM,
145-
FeatureStdExtA,
146-
FeatureStdExtF,
147-
FeatureStdExtD,
148-
FeatureStdExtC,
149-
FeatureStdExtZicntr,
150-
FeatureStdExtZihpm,
151-
FeatureStdExtZiccif,
152-
FeatureStdExtZiccrse,
153-
FeatureStdExtZiccamoa,
154-
FeatureStdExtZicclsm,
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FeatureStdExtZa64rs,
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FeatureStdExtZihintpause,
157-
FeatureStdExtZba,
158-
FeatureStdExtZbb,
159-
FeatureStdExtZbs,
160-
FeatureStdExtZic64b,
161-
FeatureStdExtZicbom,
162-
FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureStdExtZkt,
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FeatureStdExtZihintntl,
166-
FeatureStdExtZicond,
167-
FeatureStdExtZimop,
168-
FeatureStdExtZcmop,
169-
FeatureStdExtZcb,
170-
FeatureStdExtZfa,
171-
FeatureStdExtZawrs];
93+
RVA23S64BaseFeatures);
94+
95+
// RVB Profile Family
96+
97+
defvar RVB23U64Features = !listconcat(RVA20U64BaseFeatures,
98+
[FeatureStdExtZihpm,
99+
FeatureStdExtZa64rs,
100+
FeatureStdExtZihintpause,
101+
FeatureStdExtZba,
102+
FeatureStdExtZbb,
103+
FeatureStdExtZbs,
104+
FeatureStdExtZic64b,
105+
FeatureStdExtZicbom,
106+
FeatureStdExtZicbop,
107+
FeatureStdExtZicboz,
108+
FeatureStdExtZkt,
109+
FeatureStdExtZihintntl,
110+
FeatureStdExtZicond,
111+
FeatureStdExtZimop,
112+
FeatureStdExtZcmop,
113+
FeatureStdExtZcb,
114+
FeatureStdExtZfa,
115+
FeatureStdExtZawrs]);
172116

173117
defvar RVB23S64Features = !listconcat(RVB23U64Features,
174118
[FeatureStdExtZifencei,
@@ -185,6 +129,8 @@ defvar RVB23S64Features = !listconcat(RVB23U64Features,
185129
FeatureStdExtSscofpmf,
186130
FeatureStdExtSsu64xl]);
187131

132+
// RVM Profile Family
133+
188134
defvar RVM23U32Features = [Feature32Bit,
189135
FeatureStdExtI,
190136
FeatureStdExtM,
@@ -199,6 +145,22 @@ defvar RVM23U32Features = [Feature32Bit,
199145
FeatureStdExtZimop,
200146
FeatureStdExtZcmop];
201147

148+
//===----------------------------------------------------------------------===//
149+
// Profile Definitions for ISA String
150+
//===----------------------------------------------------------------------===//
151+
152+
class RISCVProfile<string name, list<SubtargetFeature> features>
153+
: SubtargetFeature<name, "Is" # NAME, "true",
154+
"RISC-V " # name # " profile", features> {
155+
// Indicates if the profile is not yet ratified, so should be treated as
156+
// experimental.
157+
bit Experimental = false;
158+
}
159+
class RISCVExperimentalProfile<string name, list<SubtargetFeature> features>
160+
: RISCVProfile<"experimental-"#name, features> {
161+
let Experimental = true;
162+
}
163+
202164
def RVI20U32 : RISCVProfile<"rvi20u32", RVI20U32Features>;
203165
def RVI20U64 : RISCVProfile<"rvi20u64", RVI20U64Features>;
204166
def RVA20U64 : RISCVProfile<"rva20u64", RVA20U64Features>;

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