[X86] Try Folding icmp of v8i32 -> fcmp of v8f32 on AVX

Fixes: #82242

The idea is that AVX doesn't support comparisons for `v8i32` so it
splits the comparison into 2x `v4i32` comparisons + reconstruction of
the `v8i32`.

By converting to a float, we can handle the comparison with 1/2
instructions (1 if we can `bitcast`, 2 if we need to cast with
`sitofp`).

The Proofs: https://alive2.llvm.org/ce/z/AJDdQ8
Timeout, but they can be reproduced locally.

Author: goldsteinn

llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

@@ -775,6 +775,13 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo() {
   } while (!Worklist.empty());
 }
 
+#if 0
+#define NOAH_DUMP(v, todo)                                                     \
+  dbgs() << "-------------------- STAGE" << #v << " ---------------------\n";     \
+  todo;
+#else
+#define NOAH_DUMP(v, todo)
+#endif
 void SelectionDAGISel::CodeGenAndEmitDAG() {
   StringRef GroupName = "sdag";
   StringRef GroupDescription = "Instruction Selection and Scheduling";
@@ -815,6 +822,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
   if (ViewDAGCombine1 && MatchFilterBB)
     CurDAG->viewGraph("dag-combine1 input for " + BlockName);
 
+  NOAH_DUMP(0, CurDAG->dump());
   // Run the DAG combiner in pre-legalize mode.
   {
     NamedRegionTimer T("combine1", "DAG Combining 1", GroupName,
@@ -838,6 +846,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
     CurDAG->viewGraph("legalize-types input for " + BlockName);
 
   bool Changed;
+  NOAH_DUMP(1, CurDAG->dump());
   {
     NamedRegionTimer T("legalize_types", "Type Legalization", GroupName,
                        GroupDescription, TimePassesIsEnabled);
@@ -896,6 +905,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
       CurDAG->VerifyDAGDivergence();
 #endif
 
+  NOAH_DUMP(2, CurDAG->dump());
     {
       NamedRegionTimer T("legalize_types2", "Type Legalization 2", GroupName,
                          GroupDescription, TimePassesIsEnabled);
@@ -915,6 +925,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
     if (ViewDAGCombineLT && MatchFilterBB)
       CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
 
+  NOAH_DUMP(3, CurDAG->dump());
     // Run the DAG combiner in post-type-legalize mode.
     {
       NamedRegionTimer T("combine_lv", "DAG Combining after legalize vectors",
@@ -936,6 +947,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
   if (ViewLegalizeDAGs && MatchFilterBB)
     CurDAG->viewGraph("legalize input for " + BlockName);
 
+  NOAH_DUMP(4, CurDAG->dump());
   {
     NamedRegionTimer T("legalize", "DAG Legalization", GroupName,
                        GroupDescription, TimePassesIsEnabled);
@@ -955,6 +967,8 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
   if (ViewDAGCombine2 && MatchFilterBB)
     CurDAG->viewGraph("dag-combine2 input for " + BlockName);
 
+
+  NOAH_DUMP(5, CurDAG->dump());
   // Run the DAG combiner in post-legalize mode.
   {
     NamedRegionTimer T("combine2", "DAG Combining 2", GroupName,
@@ -967,6 +981,8 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
                    << "'\n";
             CurDAG->dump());
 
+  NOAH_DUMP(6, CurDAG->dump());
+
 #ifndef NDEBUG
   if (TTI.hasBranchDivergence())
     CurDAG->VerifyDAGDivergence();

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -11,6 +11,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/ADT/APFloat.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Analysis/VectorUtils.h"
 #include "llvm/CodeGen/CallingConvLower.h"
@@ -21,6 +22,7 @@
 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/DerivedTypes.h"
@@ -936,6 +938,7 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedVectorElts(
                                          Depth);
 }
 
+
 // Attempt to form ext(avgfloor(A, B)) from shr(add(ext(A), ext(B)), 1).
 //      or to form ext(avgceil(A, B)) from shr(add(ext(A), ext(B), 1), 1).
 static SDValue combineShiftToAVG(SDValue Op, SelectionDAG &DAG,
@@ -2471,6 +2474,8 @@ bool TargetLowering::SimplifyDemandedBits(
     if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
                              Depth + 1))
       return true;
+
+
     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
     assert(Known.getBitWidth() == InBits && "Src width has changed?");