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[AMDGPU] Add test for GCNRegPressure tracker bug (#73786)
Add a test to document an existing problem in GCNRegPressure tracker. The upward tracker does not count the registers used (16 of them) in movrel instruction (for example V_INDIRECT_REG_WRITE_MOVREL_B32_V16). The downward tracker counts the registers but reports a mismatch: %0:L0000000000000C00 isn't found in LIS reported set
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‎llvm/test/CodeGen/AMDGPU/regpressure_printer.mir

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@@ -531,3 +531,138 @@ body: |
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%1:vgpr_32 = V_MOV_B32_e32 %0, implicit $exec
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S_NOP 0, implicit %1
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...
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---
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name: movrel
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tracksRegLiveness: true
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body: |
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; RPU-LABEL: name: movrel
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; RPU: bb.0:
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; RPU-NEXT: Live-in:
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; RPU-NEXT: SGPR VGPR
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; RPU-NEXT: 0 0
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; RPU-NEXT: 0 0 $sgpr0 = COPY $sgpr1
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; RPU-NEXT: 0 0
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; RPU-NEXT: 0 0 $sgpr2_sgpr3 = S_GETPC_B64
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; RPU-NEXT: 0 0
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; RPU-NEXT: 0 0 $sgpr1 = COPY killed $sgpr3
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; RPU-NEXT: 0 0
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; RPU-NEXT: 0 0 $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM $sgpr0_sgpr1, 0, 0
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; RPU-NEXT: 0 0
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; RPU-NEXT: 0 0 $sgpr0 = S_BUFFER_LOAD_DWORD_IMM $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0
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; RPU-NEXT: 0 0
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; RPU-NEXT: 0 0 undef %0.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
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; RPU-NEXT: 0 0
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; RPU-NEXT: 0 0 S_CMP_GT_U32 $sgpr0, 15, implicit-def $scc
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; RPU-NEXT: 0 0
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; RPU-NEXT: 0 0 S_CBRANCH_SCC1 %bb.2, implicit $scc
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; RPU-NEXT: 0 0
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; RPU-NEXT: 0 0 S_BRANCH %bb.1
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; RPU-NEXT: 0 0
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; RPU-NEXT: Live-out:
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; RPU-NEXT: Live-thr:
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; RPU-NEXT: 0 0
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; RPU-NEXT: bb.1:
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; RPU-NEXT: Live-in:
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; RPU-NEXT: SGPR VGPR
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; RPU-NEXT: 0 0
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; RPU-NEXT: 0 1 undef %0.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
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; RPU-NEXT: 0 1
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; RPU-NEXT: 0 1 $m0 = S_MOV_B32 killed $sgpr0
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; RPU-NEXT: 0 1
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; RPU-NEXT: 0 1 %0:vreg_512 = V_INDIRECT_REG_WRITE_MOVREL_B32_V16 %0:vreg_512(tied-def 0), 42, 3, implicit $m0, implicit $exec
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; RPU-NEXT: 0 1
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; RPU-NEXT: Live-out: %0:0000000000000C00
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; RPU-NEXT: Live-thr:
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; RPU-NEXT: 0 0
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; RPU-NEXT: bb.2:
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; RPU-NEXT: Live-in: %0:0000000000000C00
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; RPU-NEXT: SGPR VGPR
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; RPU-NEXT: 0 1
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; RPU-NEXT: 0 1 %1:vgpr_32 = V_CVT_F32_UBYTE0_e64 %0.sub5:vreg_512, 0, 0, implicit $exec
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; RPU-NEXT: 0 1
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; RPU-NEXT: 0 1 EXP_DONE 0, %1:vgpr_32, undef %2:vgpr_32, undef %3:vgpr_32, undef %4:vgpr_32, -1, 0, 1, implicit $exec
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; RPU-NEXT: 0 0
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; RPU-NEXT: 0 0 S_ENDPGM 0
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; RPU-NEXT: 0 0
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; RPU-NEXT: Live-out:
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; RPU-NEXT: Live-thr:
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; RPU-NEXT: 0 0
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;
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; RPD-LABEL: name: movrel
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; RPD: bb.0:
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; RPD-NEXT: Live-in:
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; RPD-NEXT: SGPR VGPR
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; RPD-NEXT: 0 0
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; RPD-NEXT: 0 0 $sgpr0 = COPY $sgpr1
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; RPD-NEXT: 0 0
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; RPD-NEXT: 0 0 $sgpr2_sgpr3 = S_GETPC_B64
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; RPD-NEXT: 0 0
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; RPD-NEXT: 0 0 $sgpr1 = COPY killed $sgpr3
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; RPD-NEXT: 0 0
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; RPD-NEXT: 0 0 $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM $sgpr0_sgpr1, 0, 0
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; RPD-NEXT: 0 0
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; RPD-NEXT: 0 0 $sgpr0 = S_BUFFER_LOAD_DWORD_IMM $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0
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; RPD-NEXT: 0 0
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; RPD-NEXT: 0 1 undef %0.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
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; RPD-NEXT: 0 1
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; RPD-NEXT: 0 1 S_CMP_GT_U32 $sgpr0, 15, implicit-def $scc
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; RPD-NEXT: 0 1
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; RPD-NEXT: 0 1 S_CBRANCH_SCC1 %bb.2, implicit $scc
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; RPD-NEXT: 0 1
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; RPD-NEXT: 0 1 S_BRANCH %bb.1
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; RPD-NEXT: 0 1
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; RPD-NEXT: Live-out: %0:0000000000000C00
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; RPD-NEXT: mis LIS:
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; RPD-NEXT: %0:L0000000000000C00 isn't found in LIS reported set
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; RPD-NEXT: Live-thr:
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; RPD-NEXT: 0 0
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; RPD-NEXT: bb.1:
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; RPD-NEXT: Live-in:
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; RPD-NEXT: SGPR VGPR
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; RPD-NEXT: 0 0
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; RPD-NEXT: 0 1 undef %0.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
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; RPD-NEXT: 0 1
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; RPD-NEXT: 0 1 $m0 = S_MOV_B32 killed $sgpr0
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; RPD-NEXT: 0 1
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; RPD-NEXT: 0 16 %0:vreg_512 = V_INDIRECT_REG_WRITE_MOVREL_B32_V16 %0:vreg_512(tied-def 0), 42, 3, implicit $m0, implicit $exec
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; RPD-NEXT: 0 1
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; RPD-NEXT: Live-out: %0:0000000000000C00
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; RPD-NEXT: Live-thr:
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; RPD-NEXT: 0 0
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; RPD-NEXT: bb.2:
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; RPD-NEXT: Live-in: %0:0000000000000C00
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; RPD-NEXT: SGPR VGPR
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; RPD-NEXT: 0 1
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; RPD-NEXT: 0 2 %1:vgpr_32 = V_CVT_F32_UBYTE0_e64 %0.sub5:vreg_512, 0, 0, implicit $exec
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; RPD-NEXT: 0 1
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; RPD-NEXT: 0 1 EXP_DONE 0, %1:vgpr_32, undef %2:vgpr_32, undef %3:vgpr_32, undef %4:vgpr_32, -1, 0, 1, implicit $exec
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; RPD-NEXT: 0 0
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; RPD-NEXT: 0 0 S_ENDPGM 0
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; RPD-NEXT: 0 0
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; RPD-NEXT: Live-out:
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; RPD-NEXT: Live-thr:
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; RPD-NEXT: 0 0
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bb.0:
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liveins: $sgpr1
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$sgpr0 = COPY $sgpr1
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$sgpr2_sgpr3 = S_GETPC_B64
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$sgpr1 = COPY killed $sgpr3
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$sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed $sgpr0_sgpr1, 0, 0
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$sgpr0 = S_BUFFER_LOAD_DWORD_IMM killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0
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undef %47.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
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S_CMP_GT_U32 $sgpr0, 15, implicit-def $scc
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S_CBRANCH_SCC1 %bb.2, implicit $scc
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S_BRANCH %bb.1
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bb.1:
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liveins: $sgpr0
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undef %47.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
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$m0 = S_MOV_B32 killed $sgpr0
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%47:vreg_512 = V_INDIRECT_REG_WRITE_MOVREL_B32_V16 %47:vreg_512, 42, 3, implicit $m0, implicit $exec
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bb.2:
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%49:vgpr_32 = V_CVT_F32_UBYTE0_e64 %47.sub5:vreg_512, 0, 0, implicit $exec
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EXP_DONE 0, %49:vgpr_32, undef %51:vgpr_32, undef %53:vgpr_32, undef %55:vgpr_32, -1, 0, 1, implicit $exec
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S_ENDPGM 0
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...

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