Address review comments.

Author: topperc

llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

@@ -216,6 +216,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
     // Use FPR64 for s64 loads on rv32.
     if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
+      assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
       OperandsMapping =
           getOperandsMapping({getFPValueMapping(64), GPRValueMapping});
       break;
@@ -242,6 +243,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
     // Use FPR64 for s64 stores on rv32.
     if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
+      assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
       OperandsMapping =
           getOperandsMapping({getFPValueMapping(64), GPRValueMapping});
       break;

llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-load-store.mir

@@ -62,18 +62,18 @@ legalized:       true
 tracksRegLiveness: true
 body:             |
   bb.1:
-    liveins: $x10, $f10_d, $f11_d
+    liveins: $x10, $f10_d
 
     ; RV32-LABEL: name: fp_store_no_def_f64
-    ; RV32: liveins: $x10, $f10_d, $f11_d
+    ; RV32: liveins: $x10, $f10_d
     ; RV32-NEXT: {{  $}}
     ; RV32-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
     ; RV32-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
     ; RV32-NEXT: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s64))
     ; RV32-NEXT: PseudoRET
     ;
     ; RV64-LABEL: name: fp_store_no_def_f64
-    ; RV64: liveins: $x10, $f10_d, $f11_d
+    ; RV64: liveins: $x10, $f10_d
     ; RV64-NEXT: {{  $}}
     ; RV64-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
     ; RV64-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d