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Pierre-vhPierre-vh
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[AMDGPU] Add & use hasNamedOperand, NFC
In a lot of places, we were just calling `getNamedOperandIdx` to check if the result was != or == to -1. This is fine in itself, but it's verbose and doesn't make the intention clear, IMHO. I added a `hasNamedOperand` and replaced all cases I could find with regexes and manually. Reviewed By: arsenm, foad Differential Revision: https://reviews.llvm.org/D137540
1 parent b5f9972 commit 7425077

14 files changed

+116
-132
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 49 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -3507,7 +3507,7 @@ bool AMDGPUAsmParser::validateConstantBusLimitations(
35073507
return true;
35083508

35093509
// Check special imm operands (used by madmk, etc)
3510-
if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1) {
3510+
if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::imm)) {
35113511
++NumLiterals;
35123512
LiteralSize = 4;
35133513
}
@@ -7897,7 +7897,7 @@ void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands,
78977897
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128A16);
78987898
if (IsGFX10Plus)
78997899
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyA16);
7900-
if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::tfe) != -1)
7900+
if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::tfe))
79017901
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
79027902
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
79037903
if (!IsGFX10Plus)
@@ -8205,9 +8205,9 @@ void cvtVOP3DstOpSelOnly(MCInst &Inst) {
82058205
const int Ops[] = { AMDGPU::OpName::src0,
82068206
AMDGPU::OpName::src1,
82078207
AMDGPU::OpName::src2 };
8208-
for (SrcNum = 0;
8209-
SrcNum < 3 && AMDGPU::getNamedOperandIdx(Opc, Ops[SrcNum]) != -1;
8210-
++SrcNum);
8208+
for (SrcNum = 0; SrcNum < 3 && AMDGPU::hasNamedOperand(Opc, Ops[SrcNum]);
8209+
++SrcNum)
8210+
;
82118211
assert(SrcNum > 0);
82128212

82138213
unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
@@ -8268,17 +8268,17 @@ void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
82688268
}
82698269
}
82708270

8271-
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::high) != -1) {
8272-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyHigh);
8273-
}
8271+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::high))
8272+
addOptionalImmOperand(Inst, Operands, OptionalIdx,
8273+
AMDGPUOperand::ImmTyHigh);
82748274

8275-
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) {
8276-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
8277-
}
8275+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
8276+
addOptionalImmOperand(Inst, Operands, OptionalIdx,
8277+
AMDGPUOperand::ImmTyClampSI);
82788278

8279-
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) {
8280-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
8281-
}
8279+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
8280+
addOptionalImmOperand(Inst, Operands, OptionalIdx,
8281+
AMDGPUOperand::ImmTyOModSI);
82828282
}
82838283

82848284
void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)
@@ -8351,7 +8351,7 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
83518351
((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
83528352
}
83538353

8354-
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) {
8354+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) {
83558355
// This instruction has src modifiers
83568356
for (unsigned E = Operands.size(); I != E; ++I) {
83578357
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
@@ -8377,13 +8377,13 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
83778377
}
83788378
}
83798379

8380-
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) {
8381-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
8382-
}
8380+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
8381+
addOptionalImmOperand(Inst, Operands, OptionalIdx,
8382+
AMDGPUOperand::ImmTyClampSI);
83838383

8384-
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) {
8385-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
8386-
}
8384+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
8385+
addOptionalImmOperand(Inst, Operands, OptionalIdx,
8386+
AMDGPUOperand::ImmTyOModSI);
83878387

83888388
// Special case v_mac_{f16, f32} and v_fmac_{f16, f32} (gfx906/gfx10+):
83898389
// it has src2 register operand that is tied to dst operand
@@ -8427,7 +8427,7 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
84278427
Inst.addOperand(Inst.getOperand(0));
84288428
}
84298429

8430-
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) {
8430+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) {
84318431
assert(!IsPacked);
84328432
Inst.addOperand(Inst.getOperand(0));
84338433
}
@@ -8885,7 +8885,7 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
88858885
unsigned Opc = Inst.getOpcode();
88868886
const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
88878887
bool HasModifiers =
8888-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1;
8888+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers);
88898889

88908890
// MAC instructions are special because they have 'old'
88918891
// operand which is not tied to dst (but assumed to be).
@@ -8943,17 +8943,17 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
89438943
llvm_unreachable("unhandled operand type");
89448944
}
89458945
}
8946-
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) {
8946+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
89478947
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
8948-
}
8949-
if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) {
8948+
8949+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
89508950
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
8951-
}
8951+
89528952
if (Desc.TSFlags & SIInstrFlags::VOP3P)
89538953
cvtVOP3P(Inst, Operands, OptionalIdx);
89548954
else if (Desc.TSFlags & SIInstrFlags::VOP3)
89558955
cvtVOP3OpSel(Inst, Operands, OptionalIdx);
8956-
else if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) {
8956+
else if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
89578957
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);
89588958
}
89598959

@@ -8966,9 +8966,10 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
89668966
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
89678967
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
89688968
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
8969-
if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::fi) != -1) {
8970-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppFi);
8971-
}
8969+
8970+
if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi))
8971+
addOptionalImmOperand(Inst, Operands, OptionalIdx,
8972+
AMDGPUOperand::ImmTyDppFi);
89728973
}
89738974
}
89748975

@@ -8977,7 +8978,7 @@ void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool I
89778978

89788979
unsigned Opc = Inst.getOpcode();
89798980
bool HasModifiers =
8980-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1;
8981+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers);
89818982
unsigned I = 1;
89828983
const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
89838984
for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
@@ -9038,7 +9039,7 @@ void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool I
90389039
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
90399040
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
90409041
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
9041-
if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::fi) != -1) {
9042+
if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi)) {
90429043
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppFi);
90439044
}
90449045
}
@@ -9180,49 +9181,46 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
91809181
SkippedVcc = false;
91819182
}
91829183

9183-
if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx10 &&
9184-
Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx9 &&
9185-
Inst.getOpcode() != AMDGPU::V_NOP_sdwa_vi) {
9184+
const unsigned Opc = Inst.getOpcode();
9185+
if (Opc != AMDGPU::V_NOP_sdwa_gfx10 && Opc != AMDGPU::V_NOP_sdwa_gfx9 &&
9186+
Opc != AMDGPU::V_NOP_sdwa_vi) {
91869187
// v_nop_sdwa_sdwa_vi/gfx9 has no optional sdwa arguments
91879188
switch (BasicInstType) {
91889189
case SIInstrFlags::VOP1:
9189-
if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
9190-
AMDGPU::OpName::clamp) != -1) {
9190+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
91919191
addOptionalImmOperand(Inst, Operands, OptionalIdx,
91929192
AMDGPUOperand::ImmTyClampSI, 0);
9193-
}
9194-
if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
9195-
AMDGPU::OpName::omod) != -1) {
9193+
9194+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
91969195
addOptionalImmOperand(Inst, Operands, OptionalIdx,
91979196
AMDGPUOperand::ImmTyOModSI, 0);
9198-
}
9199-
if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
9200-
AMDGPU::OpName::dst_sel) != -1) {
9197+
9198+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_sel))
92019199
addOptionalImmOperand(Inst, Operands, OptionalIdx,
92029200
AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD);
9203-
}
9204-
if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
9205-
AMDGPU::OpName::dst_unused) != -1) {
9201+
9202+
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_unused))
92069203
addOptionalImmOperand(Inst, Operands, OptionalIdx,
92079204
AMDGPUOperand::ImmTySdwaDstUnused,
92089205
DstUnused::UNUSED_PRESERVE);
9209-
}
9206+
92109207
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
92119208
break;
92129209

92139210
case SIInstrFlags::VOP2:
92149211
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
9215-
if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::omod) != -1) {
9212+
9213+
if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::omod))
92169214
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);
9217-
}
9215+
92189216
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD);
92199217
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, DstUnused::UNUSED_PRESERVE);
92209218
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
92219219
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD);
92229220
break;
92239221

92249222
case SIInstrFlags::VOPC:
9225-
if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::clamp) != -1)
9223+
if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::clamp))
92269224
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
92279225
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
92289226
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD);

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 15 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -740,7 +740,7 @@ DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const {
740740
DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
741741
if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
742742
STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
743-
if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
743+
if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst))
744744
// VOPC - insert clamp
745745
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
746746
} else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
@@ -804,7 +804,7 @@ bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const {
804804

805805
if (OldIdx != -1 && Desc.getOperandConstraint(
806806
OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) {
807-
assert(AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2) != -1);
807+
assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2));
808808
assert(Desc.getOperandConstraint(
809809
AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2),
810810
MCOI::OperandConstraint::TIED_TO) == DST_IDX);
@@ -838,19 +838,19 @@ DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
838838

839839
unsigned DescNumOps = MCII->get(Opc).getNumOperands();
840840
if (MI.getNumOperands() < DescNumOps &&
841-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) {
841+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
842842
auto Mods = collectVOPModifiers(MI);
843843
insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel),
844844
AMDGPU::OpName::op_sel);
845845
} else {
846846
// Insert dummy unused src modifiers.
847847
if (MI.getNumOperands() < DescNumOps &&
848-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
848+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers))
849849
insertNamedMCOperand(MI, MCOperand::createImm(0),
850850
AMDGPU::OpName::src0_modifiers);
851851

852852
if (MI.getNumOperands() < DescNumOps &&
853-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
853+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers))
854854
insertNamedMCOperand(MI, MCOperand::createImm(0),
855855
AMDGPU::OpName::src1_modifiers);
856856
}
@@ -865,7 +865,7 @@ DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const {
865865
unsigned Opc = MI.getOpcode();
866866
unsigned DescNumOps = MCII->get(Opc).getNumOperands();
867867
if (MI.getNumOperands() < DescNumOps &&
868-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) {
868+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
869869
auto Mods = collectVOPModifiers(MI);
870870
insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel),
871871
AMDGPU::OpName::op_sel);
@@ -900,9 +900,8 @@ DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
900900
assert(VDataIdx != -1);
901901
if (BaseOpcode->BVH) {
902902
// Add A16 operand for intersect_ray instructions
903-
if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) {
903+
if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::a16))
904904
addOperand(MI, MCOperand::createImm(1));
905-
}
906905
return MCDisassembler::Success;
907906
}
908907

@@ -1020,23 +1019,23 @@ DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const {
10201019
auto Mods = collectVOPModifiers(MI, true);
10211020

10221021
if (MI.getNumOperands() < DescNumOps &&
1023-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1)
1022+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in))
10241023
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in);
10251024

10261025
if (MI.getNumOperands() < DescNumOps &&
1027-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1)
1026+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel))
10281027
insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel),
10291028
AMDGPU::OpName::op_sel);
10301029
if (MI.getNumOperands() < DescNumOps &&
1031-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi) != -1)
1030+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi))
10321031
insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi),
10331032
AMDGPU::OpName::op_sel_hi);
10341033
if (MI.getNumOperands() < DescNumOps &&
1035-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo) != -1)
1034+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo))
10361035
insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo),
10371036
AMDGPU::OpName::neg_lo);
10381037
if (MI.getNumOperands() < DescNumOps &&
1039-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi) != -1)
1038+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi))
10401039
insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi),
10411040
AMDGPU::OpName::neg_hi);
10421041

@@ -1049,16 +1048,16 @@ DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const {
10491048
unsigned DescNumOps = MCII->get(Opc).getNumOperands();
10501049

10511050
if (MI.getNumOperands() < DescNumOps &&
1052-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old) != -1)
1051+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old))
10531052
insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old);
10541053

10551054
if (MI.getNumOperands() < DescNumOps &&
1056-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
1055+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers))
10571056
insertNamedMCOperand(MI, MCOperand::createImm(0),
10581057
AMDGPU::OpName::src0_modifiers);
10591058

10601059
if (MI.getNumOperands() < DescNumOps &&
1061-
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
1060+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers))
10621061
insertNamedMCOperand(MI, MCOperand::createImm(0),
10631062
AMDGPU::OpName::src1_modifiers);
10641063
return MCDisassembler::Success;

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