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-137
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2 files changed

+172
-137
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llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -931,14 +931,14 @@ static LLT getLMUL1Ty(LLT VecTy) {
931931

932932
bool RISCVLegalizerInfo::legalizeInsertSubvector(MachineInstr &MI,
933933
MachineIRBuilder &MIB) const {
934-
assert(MI.getOpcode() == TargetOpcode::G_INSERT_SUBVECTOR);
934+
GInsertSubvector &IS = cast<GInsertSubvector>(MI);
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936936
MachineRegisterInfo &MRI = *MIB.getMRI();
937937

938-
Register Dst = MI.getOperand(0).getReg();
939-
Register Src1 = MI.getOperand(1).getReg();
940-
Register Src2 = MI.getOperand(2).getReg();
941-
uint64_t Idx = MI.getOperand(3).getImm();
938+
Register Dst = IS.getOperand(0).getReg();
939+
Register Src1 = IS.getBigVec();
940+
Register Src2 = IS.getSubVec();
941+
uint64_t Idx = IS.getIndexImm();
942942

943943
LLT BigTy = MRI.getType(Src1);
944944
LLT LitTy = MRI.getType(Src2);
@@ -989,9 +989,7 @@ bool RISCVLegalizerInfo::legalizeInsertSubvector(MachineInstr &MI,
989989
getMVTForLLT(BigTy), LitTyMVT, Idx, TRI);
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991991
RISCVII::VLMUL SubVecLMUL = RISCVTargetLowering::getLMUL(getMVTForLLT(LitTy));
992-
bool IsSubVecPartReg = SubVecLMUL == RISCVII::VLMUL::LMUL_F2 ||
993-
SubVecLMUL == RISCVII::VLMUL::LMUL_F4 ||
994-
SubVecLMUL == RISCVII::VLMUL::LMUL_F8;
992+
bool IsSubVecPartReg = !RISCVVType::decodeVLMUL(SubVecLMUL).second;
995993

996994
// If the Idx has been completely eliminated and this subvector's size is a
997995
// vector register or a multiple thereof, or the surrounding elements are
@@ -1059,7 +1057,7 @@ bool RISCVLegalizerInfo::legalizeInsertSubvector(MachineInstr &MI,
10591057
// If required, insert this subvector back into the correct vector register.
10601058
// This should resolve to an INSERT_SUBREG instruction.
10611059
if (TypeSize::isKnownGT(BigTy.getSizeInBits(), InterLitTy.getSizeInBits()))
1062-
Inserted = MIB.buildInsert(BigTy, BigVec, LitVec, AlignedIdx);
1060+
Inserted = MIB.buildInsertSubvector(BigTy, BigVec, LitVec, AlignedIdx);
10631061

10641062
// We might have bitcast from a mask type: cast back to the original type if
10651063
// required.

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