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RKSimonRKSimon
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[MC][X86] addConstantComments - add mul vXi16 comments
Based on feedback from #95403 - we use multiply by constant for various lowerings (shifts, division etc.), so its very useful to printout the constants to help understand the transform involved. vXi16 multiplies are the easiest to add for this initial commit, but we can add other arithmetic instructions as follow ups when the need arises (I intend to add PMADDUBSW handling for #95403 next). I've done my best to update all test checks but there are bound to be ones that got missed that will only appear when the file is regenerated.
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‎llvm/lib/Target/X86/X86MCInstLower.cpp

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1898,6 +1898,45 @@ static void addConstantComments(const MachineInstr *MI,
18981898
break;
18991899
}
19001900

1901+
#define INSTR_CASE(Prefix, Instr, Suffix, Postfix) \
1902+
case X86::Prefix##Instr##Suffix##rm##Postfix:
1903+
1904+
#define CASE_ARITH_RM(Instr) \
1905+
INSTR_CASE(, Instr, , ) /* SSE */ \
1906+
INSTR_CASE(V, Instr, , ) /* AVX-128 */ \
1907+
INSTR_CASE(V, Instr, Y, ) /* AVX-256 */ \
1908+
INSTR_CASE(V, Instr, Z128, ) \
1909+
INSTR_CASE(V, Instr, Z128, k) \
1910+
INSTR_CASE(V, Instr, Z128, kz) \
1911+
INSTR_CASE(V, Instr, Z256, ) \
1912+
INSTR_CASE(V, Instr, Z256, k) \
1913+
INSTR_CASE(V, Instr, Z256, kz) \
1914+
INSTR_CASE(V, Instr, Z, ) \
1915+
INSTR_CASE(V, Instr, Z, k) \
1916+
INSTR_CASE(V, Instr, Z, kz)
1917+
1918+
// TODO: Add additional instructions when useful.
1919+
CASE_ARITH_RM(PMADDWD)
1920+
CASE_ARITH_RM(PMULLW)
1921+
CASE_ARITH_RM(PMULHW)
1922+
CASE_ARITH_RM(PMULHUW)
1923+
CASE_ARITH_RM(PMULHRSW) {
1924+
unsigned SrcIdx = getSrcIdx(MI, 1);
1925+
if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) {
1926+
if (C->getType()->getScalarSizeInBits() == 16) {
1927+
std::string Comment;
1928+
raw_string_ostream CS(Comment);
1929+
unsigned VectorWidth =
1930+
X86::getVectorRegisterWidth(MI->getDesc().operands()[0]);
1931+
CS << "[";
1932+
printConstant(C, VectorWidth, CS);
1933+
CS << "]";
1934+
OutStreamer.AddComment(CS.str());
1935+
}
1936+
}
1937+
break;
1938+
}
1939+
19011940
#define MASK_AVX512_CASE(Instr) \
19021941
case Instr: \
19031942
case Instr##k: \

‎llvm/test/CodeGen/X86/combine-mul.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -543,10 +543,10 @@ define <16 x i8> @PR35579(<16 x i8> %x) {
543543
; SSE: # %bb.0:
544544
; SSE-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
545545
; SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
546-
; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
546+
; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [8,1,2,1,4,1,2,1]
547547
; SSE-NEXT: pmovzxbw {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
548548
; SSE-NEXT: pand %xmm2, %xmm0
549-
; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
549+
; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [0,1,2,1,4,1,2,1]
550550
; SSE-NEXT: pand %xmm2, %xmm1
551551
; SSE-NEXT: packuswb %xmm0, %xmm1
552552
; SSE-NEXT: movdqa %xmm1, %xmm0
@@ -555,7 +555,7 @@ define <16 x i8> @PR35579(<16 x i8> %x) {
555555
; AVX-LABEL: PR35579:
556556
; AVX: # %bb.0:
557557
; AVX-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
558-
; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
558+
; AVX-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [0,1,2,1,4,1,2,1,8,1,2,1,4,1,2,1]
559559
; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
560560
; AVX-NEXT: vextracti128 $1, %ymm0, %xmm1
561561
; AVX-NEXT: vpackuswb %xmm1, %xmm0, %xmm0

‎llvm/test/CodeGen/X86/combine-sdiv.ll

Lines changed: 74 additions & 74 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/X86/combine-udiv.ll

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -471,7 +471,7 @@ define <8 x i16> @combine_vec_udiv_uniform(<8 x i16> %x) {
471471
;
472472
; AVX-LABEL: combine_vec_udiv_uniform:
473473
; AVX: # %bb.0:
474-
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
474+
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [25645,25645,25645,25645,25645,25645,25645,25645]
475475
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
476476
; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
477477
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
@@ -480,7 +480,7 @@ define <8 x i16> @combine_vec_udiv_uniform(<8 x i16> %x) {
480480
;
481481
; XOP-LABEL: combine_vec_udiv_uniform:
482482
; XOP: # %bb.0:
483-
; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
483+
; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [25645,25645,25645,25645,25645,25645,25645,25645]
484484
; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm0
485485
; XOP-NEXT: vpsrlw $1, %xmm0, %xmm0
486486
; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0
@@ -500,7 +500,7 @@ define <8 x i16> @combine_vec_udiv_nonuniform(<8 x i16> %x) {
500500
; SSE2-NEXT: psrlw $3, %xmm3
501501
; SSE2-NEXT: pandn %xmm3, %xmm1
502502
; SSE2-NEXT: por %xmm2, %xmm1
503-
; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
503+
; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [25645,61681,8195,9363,512,32769,32897,2]
504504
; SSE2-NEXT: psubw %xmm1, %xmm0
505505
; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
506506
; SSE2-NEXT: paddw %xmm1, %xmm0
@@ -515,7 +515,7 @@ define <8 x i16> @combine_vec_udiv_nonuniform(<8 x i16> %x) {
515515
; SSE41-NEXT: movdqa %xmm0, %xmm1
516516
; SSE41-NEXT: psrlw $3, %xmm1
517517
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
518-
; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
518+
; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [25645,61681,8195,9363,512,32769,32897,2]
519519
; SSE41-NEXT: psubw %xmm1, %xmm0
520520
; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
521521
; SSE41-NEXT: paddw %xmm1, %xmm0
@@ -528,18 +528,18 @@ define <8 x i16> @combine_vec_udiv_nonuniform(<8 x i16> %x) {
528528
; AVX: # %bb.0:
529529
; AVX-NEXT: vpsrlw $3, %xmm0, %xmm1
530530
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
531-
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
531+
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [25645,61681,8195,9363,512,32769,32897,2]
532532
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
533533
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
534534
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
535-
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
535+
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [4096,2048,8,u,u,2,2,u]
536536
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4],xmm1[5,6],xmm0[7]
537537
; AVX-NEXT: retq
538538
;
539539
; XOP-LABEL: combine_vec_udiv_nonuniform:
540540
; XOP: # %bb.0:
541541
; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
542-
; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
542+
; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [25645,61681,8195,9363,512,32769,32897,2]
543543
; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm0
544544
; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
545545
; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0
@@ -558,8 +558,8 @@ define <8 x i16> @combine_vec_udiv_nonuniform2(<8 x i16> %x) {
558558
; SSE2-NEXT: psrlw $1, %xmm0
559559
; SSE2-NEXT: pandn %xmm0, %xmm1
560560
; SSE2-NEXT: por %xmm2, %xmm1
561-
; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
562-
; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
561+
; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [16393,59919,58255,32787,55189,8197,52429,32789]
562+
; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [8,2048,2048,2,2048,8,2048,2]
563563
; SSE2-NEXT: movdqa %xmm1, %xmm0
564564
; SSE2-NEXT: retq
565565
;
@@ -568,22 +568,22 @@ define <8 x i16> @combine_vec_udiv_nonuniform2(<8 x i16> %x) {
568568
; SSE41-NEXT: movdqa %xmm0, %xmm1
569569
; SSE41-NEXT: psrlw $1, %xmm1
570570
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7]
571-
; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
572-
; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
571+
; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [16393,59919,58255,32787,55189,8197,52429,32789]
572+
; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [8,2048,2048,2,2048,8,2048,2]
573573
; SSE41-NEXT: retq
574574
;
575575
; AVX-LABEL: combine_vec_udiv_nonuniform2:
576576
; AVX: # %bb.0:
577577
; AVX-NEXT: vpsrlw $1, %xmm0, %xmm1
578578
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7]
579-
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
580-
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
579+
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [16393,59919,58255,32787,55189,8197,52429,32789]
580+
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [8,2048,2048,2,2048,8,2048,2]
581581
; AVX-NEXT: retq
582582
;
583583
; XOP-LABEL: combine_vec_udiv_nonuniform2:
584584
; XOP: # %bb.0:
585585
; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
586-
; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
586+
; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [16393,59919,58255,32787,55189,8197,52429,32789]
587587
; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
588588
; XOP-NEXT: retq
589589
%1 = udiv <8 x i16> %x, <i16 -34, i16 35, i16 36, i16 -37, i16 38, i16 -39, i16 40, i16 -41>
@@ -598,21 +598,21 @@ define <8 x i16> @combine_vec_udiv_nonuniform3(<8 x i16> %x) {
598598
; SSE-NEXT: psubw %xmm1, %xmm0
599599
; SSE-NEXT: psrlw $1, %xmm0
600600
; SSE-NEXT: paddw %xmm1, %xmm0
601-
; SSE-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
601+
; SSE-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [16384,4096,4096,4096,4096,2048,2048,1024]
602602
; SSE-NEXT: retq
603603
;
604604
; AVX-LABEL: combine_vec_udiv_nonuniform3:
605605
; AVX: # %bb.0:
606-
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
606+
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [9363,25645,18351,12137,2115,23705,1041,517]
607607
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
608608
; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
609609
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
610-
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
610+
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [16384,4096,4096,4096,4096,2048,2048,1024]
611611
; AVX-NEXT: retq
612612
;
613613
; XOP-LABEL: combine_vec_udiv_nonuniform3:
614614
; XOP: # %bb.0:
615-
; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
615+
; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [9363,25645,18351,12137,2115,23705,1041,517]
616616
; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm0
617617
; XOP-NEXT: vpsrlw $1, %xmm0, %xmm0
618618
; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0
@@ -687,7 +687,7 @@ define <8 x i16> @pr38477(<8 x i16> %a0) {
687687
; SSE2-NEXT: pmulhuw %xmm0, %xmm1
688688
; SSE2-NEXT: movdqa %xmm0, %xmm2
689689
; SSE2-NEXT: psubw %xmm1, %xmm2
690-
; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
690+
; SSE2-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [u,32768,0,0,0,0,0,32768]
691691
; SSE2-NEXT: paddw %xmm1, %xmm2
692692
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535,65535,65535,0,65535]
693693
; SSE2-NEXT: pandn %xmm2, %xmm1
@@ -706,7 +706,7 @@ define <8 x i16> @pr38477(<8 x i16> %a0) {
706706
; SSE41-NEXT: pmulhuw %xmm0, %xmm1
707707
; SSE41-NEXT: movdqa %xmm0, %xmm2
708708
; SSE41-NEXT: psubw %xmm1, %xmm2
709-
; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
709+
; SSE41-NEXT: pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [u,32768,0,0,0,0,0,32768]
710710
; SSE41-NEXT: paddw %xmm1, %xmm2
711711
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [u,1024,1024,16,4,1024,u,4096]
712712
; SSE41-NEXT: pmulhuw %xmm2, %xmm1
@@ -716,20 +716,20 @@ define <8 x i16> @pr38477(<8 x i16> %a0) {
716716
;
717717
; AVX-LABEL: pr38477:
718718
; AVX: # %bb.0:
719-
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
719+
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [u,4957,57457,4103,16385,35545,2048,2115]
720720
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm2
721-
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
721+
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [u,32768,0,0,0,0,0,32768]
722722
; AVX-NEXT: vpaddw %xmm1, %xmm2, %xmm1
723-
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2
723+
; AVX-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2 # [u,1024,1024,16,4,1024,u,4096]
724724
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3,4,5],xmm1[6],xmm2[7]
725725
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
726726
; AVX-NEXT: retq
727727
;
728728
; XOP-LABEL: pr38477:
729729
; XOP: # %bb.0:
730-
; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
730+
; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [u,4957,57457,4103,16385,35545,2048,2115]
731731
; XOP-NEXT: vpsubw %xmm1, %xmm0, %xmm2
732-
; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
732+
; XOP-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [u,32768,0,0,0,0,0,32768]
733733
; XOP-NEXT: vpaddw %xmm1, %xmm2, %xmm1
734734
; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
735735
; XOP-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]

‎llvm/test/CodeGen/X86/dagcombine-shifts.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -394,7 +394,7 @@ define <4 x i32> @shift_zext_shl_vec(<4 x i8> %x) nounwind {
394394
; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
395395
; X64-NEXT: pxor %xmm1, %xmm1
396396
; X64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
397-
; X64-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
397+
; X64-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [512,256,128,64,u,u,u,u]
398398
; X64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
399399
; X64-NEXT: retq
400400
%a = and <4 x i8> %x, <i8 64, i8 63, i8 31, i8 23>

‎llvm/test/CodeGen/X86/dpbusd_const.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ define i32 @mul_4xi8_zc_exceed(<4 x i8> %a, i32 %c) {
77
; ALL-LABEL: mul_4xi8_zc_exceed:
88
; ALL: # %bb.0: # %entry
99
; ALL-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
10-
; ALL-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
10+
; ALL-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [0,0,1,0,2,0,128,0]
1111
; ALL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
1212
; ALL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
1313
; ALL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
@@ -148,7 +148,7 @@ define i32 @mul_4xi8_cs_exceed(<4 x i8> %a, i32 %c) {
148148
; ALL-LABEL: mul_4xi8_cs_exceed:
149149
; ALL: # %bb.0: # %entry
150150
; ALL-NEXT: vpmovsxbd %xmm0, %xmm0
151-
; ALL-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
151+
; ALL-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [0,0,1,0,2,0,256,0]
152152
; ALL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
153153
; ALL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
154154
; ALL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]

‎llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1008,7 +1008,7 @@ define <2 x half> @fmul_pow_shl_cnt_vec_fail_to_large(<2 x i16> %cnt) nounwind {
10081008
; CHECK-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
10091009
; CHECK-SSE-NEXT: cvttps2dq %xmm0, %xmm0
10101010
; CHECK-SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,2,2,3,4,5,6,7]
1011-
; CHECK-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
1011+
; CHECK-SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [2,2,u,u,u,u,u,u]
10121012
; CHECK-SSE-NEXT: pxor %xmm0, %xmm0
10131013
; CHECK-SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
10141014
; CHECK-SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill

‎llvm/test/CodeGen/X86/freeze-binary.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -329,12 +329,12 @@ define i32 @freeze_mul_nsw(i32 %a0) nounwind {
329329
define <8 x i16> @freeze_mul_vec(<8 x i16> %a0) nounwind {
330330
; X86-LABEL: freeze_mul_vec:
331331
; X86: # %bb.0:
332-
; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
332+
; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # [4,6,6,4,4,6,6,4]
333333
; X86-NEXT: retl
334334
;
335335
; X64-LABEL: freeze_mul_vec:
336336
; X64: # %bb.0:
337-
; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
337+
; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [4,6,6,4,4,6,6,4]
338338
; X64-NEXT: retq
339339
%x = mul <8 x i16> %a0, <i16 1, i16 2, i16 3, i16 4, i16 4, i16 3, i16 2, i16 1>
340340
%y = freeze <8 x i16> %x
@@ -345,14 +345,14 @@ define <8 x i16> @freeze_mul_vec(<8 x i16> %a0) nounwind {
345345
define <8 x i16> @freeze_mul_vec_undef(<8 x i16> %a0) nounwind {
346346
; X86-LABEL: freeze_mul_vec_undef:
347347
; X86: # %bb.0:
348-
; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
349-
; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
348+
; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # [1,2,3,4,4,3,0,1]
349+
; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # [4,3,2,1,1,2,u,4]
350350
; X86-NEXT: retl
351351
;
352352
; X64-LABEL: freeze_mul_vec_undef:
353353
; X64: # %bb.0:
354-
; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
355-
; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
354+
; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [1,2,3,4,4,3,0,1]
355+
; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [4,3,2,1,1,2,u,4]
356356
; X64-NEXT: retq
357357
%x = mul <8 x i16> %a0, <i16 1, i16 2, i16 3, i16 4, i16 4, i16 3, i16 undef, i16 1>
358358
%y = freeze <8 x i16> %x

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