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[fixup] Remove AArch64ISD::FA{MIN,MAX}_PRED
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-170
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4 files changed

+4
-170
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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2735,8 +2735,6 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
27352735
MAKE_CASE(AArch64ISD::FMINNMV_PRED)
27362736
MAKE_CASE(AArch64ISD::FMUL_PRED)
27372737
MAKE_CASE(AArch64ISD::FSUB_PRED)
2738-
MAKE_CASE(AArch64ISD::FAMAX_PRED)
2739-
MAKE_CASE(AArch64ISD::FAMIN_PRED)
27402738
MAKE_CASE(AArch64ISD::RDSVL)
27412739
MAKE_CASE(AArch64ISD::BIC)
27422740
MAKE_CASE(AArch64ISD::CBZ)
@@ -22134,12 +22132,6 @@ static SDValue performIntrinsicCombine(SDNode *N,
2213422132
AArch64CC::LAST_ACTIVE);
2213522133
case Intrinsic::aarch64_sve_whilelo:
2213622134
return tryCombineWhileLo(N, DCI, Subtarget);
22137-
case Intrinsic::aarch64_sve_famax_u:
22138-
return DAG.getNode(AArch64ISD::FAMAX_PRED, SDLoc(N), N->getValueType(0),
22139-
N->getOperand(1), N->getOperand(2), N->getOperand(3));
22140-
case Intrinsic::aarch64_sve_famin_u:
22141-
return DAG.getNode(AArch64ISD::FAMIN_PRED, SDLoc(N), N->getValueType(0),
22142-
N->getOperand(1), N->getOperand(2), N->getOperand(3));
2214322135
}
2214422136
return SDValue();
2214522137
}

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -135,8 +135,6 @@ enum NodeType : unsigned {
135135
UDIV_PRED,
136136
UMAX_PRED,
137137
UMIN_PRED,
138-
FAMAX_PRED,
139-
FAMIN_PRED,
140138

141139
// Unpredicated vector instructions
142140
BIC,

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -218,9 +218,6 @@ def AArch64fsub_p_contract : PatFrag<(ops node:$op1, node:$op2, node:$op3),
218218
return N->getFlags().hasAllowContract();
219219
}]>;
220220

221-
def AArch64famax_p : SDNode<"AArch64ISD::FAMAX_PRED", SDT_AArch64Arith>;
222-
def AArch64famin_p : SDNode<"AArch64ISD::FAMIN_PRED", SDT_AArch64Arith>;
223-
224221
def SDT_AArch64Arith_Imm : SDTypeProfile<1, 3, [
225222
SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVT<3,i32>,
226223
SDTCVecEltisVT<1,i1>, SDTCisSameAs<0,2>
@@ -486,8 +483,6 @@ def AArch64fminnm_m1 : VSelectCommPredOrPassthruPatFrags<int_aarch64_sve_fminnm,
486483
def AArch64fmaxnm_m1 : VSelectCommPredOrPassthruPatFrags<int_aarch64_sve_fmaxnm, AArch64fmaxnm_p>;
487484
def AArch64fmin_m1 : VSelectCommPredOrPassthruPatFrags<int_aarch64_sve_fmin, AArch64fmin_p>;
488485
def AArch64fmax_m1 : VSelectCommPredOrPassthruPatFrags<int_aarch64_sve_fmax, AArch64fmax_p>;
489-
def AArch64famax_m1 : VSelectCommPredOrPassthruPatFrags<int_aarch64_sve_famax, AArch64famax_p>;
490-
def AArch64famin_m1 : VSelectCommPredOrPassthruPatFrags<int_aarch64_sve_famin, AArch64famin_p>;
491486

492487
def AArch64fadd : PatFrags<(ops node:$op1, node:$op2),
493488
[(fadd node:$op1, node:$op2),
@@ -723,8 +718,8 @@ let Predicates = [HasSVEorSME] in {
723718
} // End HasSVEorSME
724719

725720
let Predicates = [HasSVE2orSME2, HasFAMINMAX] in {
726-
defm FAMAX_ZPZZ : sve_fp_bin_pred_hfd<AArch64famax_p>;
727-
defm FAMIN_ZPZZ : sve_fp_bin_pred_hfd<AArch64famin_p>;
721+
defm FAMAX_ZPZZ : sve_fp_bin_pred_hfd<int_aarch64_sve_famax_u>;
722+
defm FAMIN_ZPZZ : sve_fp_bin_pred_hfd<int_aarch64_sve_famin_u>;
728723
}
729724

730725
let Predicates = [HasSVEorSME, UseExperimentalZeroingPseudos] in {
@@ -4194,8 +4189,8 @@ defm FCVTNT_Z2Z_StoB : sve2_fp8_down_cvt_single<0b11, "fcvtnt", ZZ_s_mul_r>;
41944189

41954190
let Predicates = [HasSVE2orSME2, HasFAMINMAX] in {
41964191
// FP8 Arithmetic - Predicated Group
4197-
defm FAMIN_ZPmZ : sve_fp_2op_p_zds<0b1111, "famin", "FAMIN_ZPZZ", AArch64famin_m1, DestructiveBinaryComm>;
4198-
defm FAMAX_ZPmZ : sve_fp_2op_p_zds<0b1110, "famax", "FAMAX_ZPZZ", AArch64famax_m1, DestructiveBinaryComm>;
4192+
defm FAMIN_ZPmZ : sve_fp_2op_p_zds<0b1111, "famin", "FAMIN_ZPZZ", int_aarch64_sve_famin, DestructiveBinaryComm>;
4193+
defm FAMAX_ZPmZ : sve_fp_2op_p_zds<0b1110, "famax", "FAMAX_ZPZZ", int_aarch64_sve_famax, DestructiveBinaryComm>;
41994194
} // End HasSVE2orSME2, HasFAMINMAX
42004195

42014196
let Predicates = [HasSSVE_FP8FMA] in {

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-faminmax.ll

Lines changed: 0 additions & 151 deletions
Original file line numberDiff line numberDiff line change
@@ -112,155 +112,4 @@ define <vscale x 2 x double> @famax_u_f64(<vscale x 2 x i1> %pg, <vscale x 2 x d
112112
ret <vscale x 2 x double> %r
113113
}
114114

115-
define <vscale x 8 x half> @select_famin_f16a(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
116-
; CHECK-LABEL: select_famin_f16a:
117-
; CHECK: // %bb.0:
118-
; CHECK-NEXT: famin z0.h, p0/m, z0.h, z1.h
119-
; CHECK-NEXT: ret
120-
%all.true = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
121-
%m = call <vscale x 8 x half> @llvm.aarch64.sve.famin.u.nxv8f16(<vscale x 8 x i1> %all.true, <vscale x 8 x half> %a, <vscale x 8 x half> %b)
122-
%r = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %m, <vscale x 8 x half> %a
123-
ret <vscale x 8 x half> %r
124-
}
125-
126-
define <vscale x 8 x half> @select_famin_f16b(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
127-
; CHECK-LABEL: select_famin_f16b:
128-
; CHECK: // %bb.0:
129-
; CHECK-NEXT: famin z0.h, p0/m, z0.h, z1.h
130-
; CHECK-NEXT: ret
131-
%all.true = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
132-
%m = call <vscale x 8 x half> @llvm.aarch64.sve.famin.u.nxv8f16(<vscale x 8 x i1> %all.true, <vscale x 8 x half> %b, <vscale x 8 x half> %a)
133-
%r = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %m, <vscale x 8 x half> %a
134-
ret <vscale x 8 x half> %r
135-
}
136-
137-
define <vscale x 4 x float> @select_famin_f32a(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
138-
; CHECK-LABEL: select_famin_f32a:
139-
; CHECK: // %bb.0:
140-
; CHECK-NEXT: famin z0.s, p0/m, z0.s, z1.s
141-
; CHECK-NEXT: ret
142-
%all.true = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
143-
%m = call <vscale x 4 x float> @llvm.aarch64.sve.famin.u.nxv4f32(<vscale x 4 x i1> %all.true, <vscale x 4 x float> %a, <vscale x 4 x float> %b)
144-
%r = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %m, <vscale x 4 x float> %a
145-
ret <vscale x 4 x float> %r
146-
}
147-
148-
define <vscale x 4 x float> @select_famin_f32b(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
149-
; CHECK-LABEL: select_famin_f32b:
150-
; CHECK: // %bb.0:
151-
; CHECK-NEXT: famin z0.s, p0/m, z0.s, z1.s
152-
; CHECK-NEXT: ret
153-
%all.true = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
154-
%m = call <vscale x 4 x float> @llvm.aarch64.sve.famin.u.nxv4f32(<vscale x 4 x i1> %all.true, <vscale x 4 x float> %b, <vscale x 4 x float> %a)
155-
%r = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %m, <vscale x 4 x float> %a
156-
ret <vscale x 4 x float> %r
157-
}
158-
159-
define <vscale x 2 x double> @select_famin_f64a(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
160-
; CHECK-LABEL: select_famin_f64a:
161-
; CHECK: // %bb.0:
162-
; CHECK-NEXT: famin z0.d, p0/m, z0.d, z1.d
163-
; CHECK-NEXT: ret
164-
%all.true = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
165-
%m = call <vscale x 2 x double> @llvm.aarch64.sve.famin.u.nxv2f64(<vscale x 2 x i1> %all.true, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
166-
%r = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %m, <vscale x 2 x double> %a
167-
ret <vscale x 2 x double> %r
168-
}
169-
170-
define <vscale x 2 x double> @select_famin_f64b(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
171-
; CHECK-LABEL: select_famin_f64b:
172-
; CHECK: // %bb.0:
173-
; CHECK-NEXT: famin z0.d, p0/m, z0.d, z1.d
174-
; CHECK-NEXT: ret
175-
%all.true = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
176-
%m = call <vscale x 2 x double> @llvm.aarch64.sve.famin.u.nxv2f64(<vscale x 2 x i1> %all.true, <vscale x 2 x double> %b, <vscale x 2 x double> %a)
177-
%r = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %m, <vscale x 2 x double> %a
178-
ret <vscale x 2 x double> %r
179-
}
180-
181-
182-
define <vscale x 8 x half> @select_famax_f16a(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
183-
; CHECK-LABEL: select_famax_f16a:
184-
; CHECK: // %bb.0:
185-
; CHECK-NEXT: famax z0.h, p0/m, z0.h, z1.h
186-
; CHECK-NEXT: ret
187-
%all.true = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
188-
%m = call <vscale x 8 x half> @llvm.aarch64.sve.famax.u.nxv8f16(<vscale x 8 x i1> %all.true, <vscale x 8 x half> %a, <vscale x 8 x half> %b)
189-
%r = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %m, <vscale x 8 x half> %a
190-
ret <vscale x 8 x half> %r
191-
}
192-
193-
define <vscale x 8 x half> @select_famax_f16b(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
194-
; CHECK-LABEL: select_famax_f16b:
195-
; CHECK: // %bb.0:
196-
; CHECK-NEXT: famax z0.h, p0/m, z0.h, z1.h
197-
; CHECK-NEXT: ret
198-
%all.true = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
199-
%m = call <vscale x 8 x half> @llvm.aarch64.sve.famax.u.nxv8f16(<vscale x 8 x i1> %all.true, <vscale x 8 x half> %b, <vscale x 8 x half> %a)
200-
%r = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %m, <vscale x 8 x half> %a
201-
ret <vscale x 8 x half> %r
202-
}
203-
204-
define <vscale x 4 x float> @select_famax_f32a(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
205-
; CHECK-LABEL: select_famax_f32a:
206-
; CHECK: // %bb.0:
207-
; CHECK-NEXT: famax z0.s, p0/m, z0.s, z1.s
208-
; CHECK-NEXT: ret
209-
%all.true = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
210-
%m = call <vscale x 4 x float> @llvm.aarch64.sve.famax.u.nxv4f32(<vscale x 4 x i1> %all.true, <vscale x 4 x float> %a, <vscale x 4 x float> %b)
211-
%r = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %m, <vscale x 4 x float> %a
212-
ret <vscale x 4 x float> %r
213-
}
214-
215-
define <vscale x 4 x float> @select_famax_f32b(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
216-
; CHECK-LABEL: select_famax_f32b:
217-
; CHECK: // %bb.0:
218-
; CHECK-NEXT: famax z0.s, p0/m, z0.s, z1.s
219-
; CHECK-NEXT: ret
220-
%all.true = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
221-
%m = call <vscale x 4 x float> @llvm.aarch64.sve.famax.u.nxv4f32(<vscale x 4 x i1> %all.true, <vscale x 4 x float> %b, <vscale x 4 x float> %a)
222-
%r = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %m, <vscale x 4 x float> %a
223-
ret <vscale x 4 x float> %r
224-
}
225-
226-
define <vscale x 2 x double> @select_famax_f64a(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
227-
; CHECK-LABEL: select_famax_f64a:
228-
; CHECK: // %bb.0:
229-
; CHECK-NEXT: famax z0.d, p0/m, z0.d, z1.d
230-
; CHECK-NEXT: ret
231-
%all.true = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
232-
%m = call <vscale x 2 x double> @llvm.aarch64.sve.famax.u.nxv2f64(<vscale x 2 x i1> %all.true, <vscale x 2 x double> %a, <vscale x 2 x double> %b)
233-
%r = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %m, <vscale x 2 x double> %a
234-
ret <vscale x 2 x double> %r
235-
}
236-
237-
define <vscale x 2 x double> @select_famax_f64b(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
238-
; CHECK-LABEL: select_famax_f64b:
239-
; CHECK: // %bb.0:
240-
; CHECK-NEXT: famax z0.d, p0/m, z0.d, z1.d
241-
; CHECK-NEXT: ret
242-
%all.true = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
243-
%m = call <vscale x 2 x double> @llvm.aarch64.sve.famax.u.nxv2f64(<vscale x 2 x i1> %all.true, <vscale x 2 x double> %b, <vscale x 2 x double> %a)
244-
%r = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %m, <vscale x 2 x double> %a
245-
ret <vscale x 2 x double> %r
246-
}
247-
248-
declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)
249-
declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
250-
declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)
251-
252-
declare <vscale x 8 x half> @llvm.aarch64.sve.famin.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
253-
declare <vscale x 4 x float> @llvm.aarch64.sve.famin.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
254-
declare <vscale x 2 x double> @llvm.aarch64.sve.famin.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
255-
declare <vscale x 8 x half> @llvm.aarch64.sve.famin.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
256-
declare <vscale x 4 x float> @llvm.aarch64.sve.famin.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
257-
declare <vscale x 2 x double> @llvm.aarch64.sve.famin.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
258-
259-
declare <vscale x 8 x half> @llvm.aarch64.sve.famax.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
260-
declare <vscale x 4 x float> @llvm.aarch64.sve.famax.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
261-
declare <vscale x 2 x double> @llvm.aarch64.sve.famax.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
262-
declare <vscale x 8 x half> @llvm.aarch64.sve.famax.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
263-
declare <vscale x 4 x float> @llvm.aarch64.sve.famax.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
264-
declare <vscale x 2 x double> @llvm.aarch64.sve.famax.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
265-
266115
attributes #0 = { nounwind "target-features" = "+faminmax" }

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