Skip to content

Commit 755c28a

Browse files
authored
[GISel][Mips] Infer alignment when creating memory operand for G_VASTART. (#74004)
1 parent 6402706 commit 755c28a

File tree

2 files changed

+4
-3
lines changed

2 files changed

+4
-3
lines changed

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,7 @@
8181
#include "llvm/Support/raw_ostream.h"
8282
#include "llvm/Target/TargetIntrinsicInfo.h"
8383
#include "llvm/Target/TargetMachine.h"
84+
#include "llvm/Transforms/Utils/Local.h"
8485
#include "llvm/Transforms/Utils/MemoryOpRemark.h"
8586
#include <algorithm>
8687
#include <cassert>
@@ -2067,12 +2068,12 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
20672068
auto &TLI = *MF->getSubtarget().getTargetLowering();
20682069
Value *Ptr = CI.getArgOperand(0);
20692070
unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8;
2071+
Align Alignment = getKnownAlignment(Ptr, *DL);
20702072

2071-
// FIXME: Get alignment
20722073
MIRBuilder.buildInstr(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*Ptr)})
20732074
.addMemOperand(MF->getMachineMemOperand(MachinePointerInfo(Ptr),
20742075
MachineMemOperand::MOStore,
2075-
ListSize, Align(1)));
2076+
ListSize, Alignment));
20762077
return true;
20772078
}
20782079
case Intrinsic::dbg_value: {

llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ define void @testVaCopyArg(ptr %fmt, ...) {
2727
; MIPS32-NEXT: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.2.aq
2828
; MIPS32-NEXT: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.3.s
2929
; MIPS32-NEXT: G_STORE [[COPY]](p0), [[FRAME_INDEX3]](p0) :: (store (p0) into %ir.fmt.addr)
30-
; MIPS32-NEXT: G_VASTART [[FRAME_INDEX4]](p0) :: (store (s32) into %ir.ap, align 1)
30+
; MIPS32-NEXT: G_VASTART [[FRAME_INDEX4]](p0) :: (store (s32) into %ir.ap)
3131
; MIPS32-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[FRAME_INDEX5]](p0), [[FRAME_INDEX4]](p0)
3232
; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX5]](p0) :: (dereferenceable load (p0) from %ir.aq)
3333
; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4

0 commit comments

Comments
 (0)