Reapply "Move assertion for AdjustsStack from PEI to MachineVerifier (#85698)"

- The check is now actually done in both PEI and the MachineVerifier.
- More .mir tests trivially updated with "adjustsStack: true" as needed.

Author: JonPsson1

llvm/lib/CodeGen/MachineVerifier.cpp

@@ -3697,6 +3697,9 @@ void MachineVerifier::verifyStackFrame() {
       if (I.getOpcode() == FrameSetupOpcode) {
         if (BBState.ExitIsSetup)
           report("FrameSetup is after another FrameSetup", &I);
+        if (!MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
+          report("AdjustsStack not set in presence of a frame pseudo "
+                 "instruction.", &I);
         BBState.ExitValue -= TII->getFrameTotalSize(I);
         BBState.ExitIsSetup = true;
       }
@@ -3712,6 +3715,9 @@ void MachineVerifier::verifyStackFrame() {
           errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
               << AbsSPAdj << ">.\n";
         }
+        if (!MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
+          report("AdjustsStack not set in presence of a frame pseudo "
+                 "instruction.", &I);
         BBState.ExitValue += Size;
         BBState.ExitIsSetup = false;
       }

llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir

@@ -3,6 +3,8 @@
 ---
 name:            func
 tracksRegLiveness: true
+frameInfo:
+  adjustsStack:    true
 body:             |
   bb.0:
     liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6

llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir

@@ -22,6 +22,7 @@
 name:            inst_stores_to_dead_spill_implicit_def_impdef
 tracksRegLiveness: true
 frameInfo:
+  adjustsStack:    true
   hasCalls:        true
 body:             |
   bb.0:
@@ -59,6 +60,7 @@ body:             |
 name:            inst_stores_to_dead_spill_movimm_impdef
 tracksRegLiveness: true
 frameInfo:
+  adjustsStack:    true
   hasCalls:        true
 body:             |
   bb.0:

llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir

@@ -4,6 +4,8 @@
 ---
 name:            widget
 tracksRegLiveness: true
+frameInfo:
+  adjustsStack:    true
 jumpTable:
   kind:            label-difference32
   entries:

llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir

@@ -8,6 +8,8 @@
 ---
 name:            restore_undef_copy_use
 tracksRegLiveness: true
+frameInfo:
+  adjustsStack:    true
 machineFunctionInfo:
   maxKernArgAlign: 1
   isEntryFunction: true

llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir

@@ -13,6 +13,7 @@
 name:            greedy_fail_alloc_sgpr1024_spill
 tracksRegLiveness: true
 frameInfo:
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo:
   explicitKernArgSize: 16

llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir

@@ -24,6 +24,7 @@ registers:
   - { id: 10, class: sreg_64_xexec, preferred-register: '$vcc' }
 frameInfo:
   maxAlignment:    1
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo:
   maxKernArgAlign: 1

llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir

@@ -181,6 +181,8 @@ legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
+frameInfo:
+  adjustsStack:    true
 liveins:
   - { reg: '$vgpr0', virtual-reg: '%0' }
   - { reg: '$vgpr1', virtual-reg: '%1' }

llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir

@@ -78,6 +78,7 @@
 name:            sgpr_spill_wrong_stack_id
 tracksRegLiveness: true
 frameInfo:
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo:
   scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3

llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir

@@ -21,6 +21,7 @@
 name:            kernel
 tracksRegLiveness: true
 frameInfo:
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo:
   isEntryFunction: true

llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir

@@ -20,6 +20,7 @@ name:            undef_identity_copy
 tracksRegLiveness: true
 frameInfo:
   maxAlignment:    4
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo:
   isEntryFunction: true

llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir

@@ -86,6 +86,8 @@
 ---
 name:            main
 exposesReturnsTwice: true
+frameInfo:
+  adjustsStack:    true
 stack:
   - { id: 0, name: P0, size: 80, alignment: 8, local-offset: -80 }
   - { id: 1, name: jb1, size: 160, alignment: 8, local-offset: -240 }

llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir

@@ -135,7 +135,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    0
-  adjustsStack:    false
+  adjustsStack:    true
   hasCalls:        true
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false

llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir

@@ -25,6 +25,8 @@
 name:            autogen_SD21418
 alignment:       4
 tracksRegLiveness: true
+frameInfo:
+  adjustsStack:    true
 registers:       
   - { id: 0, class: vr128bit }
   - { id: 1, class: vr128bit }

llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir

@@ -157,6 +157,7 @@ registers:
   - { id: 129, class: grx32bit }
   - { id: 130, class: fp64bit }
 frameInfo:
+  adjustsStack:    true
   hasCalls:        true
 body:             |
   bb.0:

llvm/test/CodeGen/SystemZ/int-cmp-56.mir

@@ -48,6 +48,7 @@ liveins:
   - { reg: '$r2d', virtual-reg: '%0' }
 frameInfo:
   maxAlignment:    1
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |
@@ -125,6 +126,7 @@ liveins:
   - { reg: '$r2d', virtual-reg: '%0' }
 frameInfo:
   maxAlignment:    1
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |
@@ -202,6 +204,7 @@ liveins:
   - { reg: '$r2d', virtual-reg: '%0' }
 frameInfo:
   maxAlignment:    1
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |
@@ -279,6 +282,7 @@ liveins:
   - { reg: '$r2d', virtual-reg: '%0' }
 frameInfo:
   maxAlignment:    1
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |

llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir

@@ -49,6 +49,8 @@ body:             |
 ---
 name:            segfault
 tracksRegLiveness: true
+frameInfo:
+  adjustsStack:    true
 liveins:         []
 body:             |
   ; CHECK-LABEL: name: segfault

llvm/test/CodeGen/X86/callbr-asm-kill.mir

@@ -45,6 +45,7 @@ liveins:
   - { reg: '$rsi', virtual-reg: '%3' }
 frameInfo:
   maxAlignment:    1
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |

llvm/test/CodeGen/X86/late-remat-update.mir

@@ -66,6 +66,7 @@ registers:
 liveins:         
   - { reg: '$edi', virtual-reg: '%0' }
 frameInfo:       
+  adjustsStack:    true
   hasCalls:        true
 body:             |
   bb.0.entry:

llvm/test/CodeGen/X86/limit-split-cost.mir

@@ -86,6 +86,7 @@ registers:
 liveins:         
   - { reg: '$edi', virtual-reg: '%0' }
 frameInfo:       
+  adjustsStack:    true
   hasCalls:        true
 body:             |
   bb.0.entry:

llvm/test/CodeGen/X86/regalloc-copy-hints.mir

@@ -103,6 +103,7 @@ registers:
   - { id: 82, class: gr32 }
 frameInfo:       
   maxAlignment:    4
+  adjustsStack:    true
   hasCalls:        true
 fixedStack:      
   - { id: 0, size: 4, alignment: 4, stack-id: default, isImmutable: true }

llvm/test/CodeGen/X86/statepoint-fastregalloc.mir

@@ -6,6 +6,8 @@
 ---
 name:            test_relocate
 tracksRegLiveness: true
+frameInfo:
+  adjustsStack:    true
 body:             |
   bb.0.entry:
     liveins: $rdi
@@ -25,6 +27,8 @@ body:             |
 ---
 name:            test_relocate_multi_regmasks
 tracksRegLiveness: true
+frameInfo:
+  adjustsStack:    true
 body:             |
   bb.0.entry:
     liveins: $rdi

llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir

@@ -231,7 +231,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
-  adjustsStack:    false
+  adjustsStack:    true
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295

llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir

@@ -398,7 +398,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
-  adjustsStack:    false
+  adjustsStack:    true
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295

llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir

@@ -175,7 +175,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    4
-  adjustsStack:    false
+  adjustsStack:    true
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295

llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir

@@ -226,7 +226,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    4
-  adjustsStack:    false
+  adjustsStack:    true
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295

llvm/test/CodeGen/X86/statepoint-invoke-ra.mir

@@ -172,7 +172,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    4
-  adjustsStack:    false
+  adjustsStack:    true
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295

llvm/test/CodeGen/X86/statepoint-vreg-folding.mir

@@ -114,7 +114,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    8
-  adjustsStack:    false
+  adjustsStack:    true
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295

llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir

@@ -100,6 +100,7 @@ registers:
   - { id: 38, class: gr8 }
 frameInfo:
   maxAlignment:    1
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |

llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir

@@ -87,6 +87,7 @@ liveins:
   - { reg: '$edi', virtual-reg: '%0' }
   - { reg: '$xmm0', virtual-reg: '%1' }
 frameInfo:
+  adjustsStack:    true
   hasCalls:        true
 body:             |
   bb.0.if.then:

llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir

@@ -97,6 +97,7 @@ liveins:
   - { reg: '$esi', virtual-reg: '%4' }
 frameInfo:
   maxAlignment:    1
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |

llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir

@@ -106,6 +106,7 @@ liveins:
   - { reg: '$rsi', virtual-reg: '%5' }
 frameInfo:
   maxAlignment:    1
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |

llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir

@@ -70,6 +70,7 @@ liveins:
   - { reg: '$esi', virtual-reg: '%2' }
 frameInfo:
   maxAlignment:    1
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |

llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir

@@ -71,6 +71,7 @@ liveins:
   - { reg: '$esi', virtual-reg: '%2' }
 frameInfo:
   maxAlignment:    1
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |

llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir

@@ -65,6 +65,7 @@ liveins:
   - { reg: '$esi', virtual-reg: '%2' }
 frameInfo:
   maxAlignment:    1
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |

llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir

@@ -94,6 +94,7 @@ liveins:
   - { reg: '$esi', virtual-reg: '%2' }
 frameInfo:
   maxAlignment:    1
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |

llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir

@@ -106,6 +106,7 @@ liveins:
   - { reg: '$rdi', virtual-reg: '%15' }
 frameInfo:
   maxAlignment:    8
+  adjustsStack:    true
   hasCalls:        true
 stack:
   - { id: 0, size: 8, alignment: 8 }

llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir

@@ -113,6 +113,7 @@ liveins:
   - { reg: '$rdi', virtual-reg: '%2' }
   - { reg: '$esi', virtual-reg: '%4' }
 frameInfo:
+  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |

llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir

@@ -72,6 +72,8 @@
 name:            fn2
 alignment:       4
 tracksRegLiveness: true
+frameInfo:
+  adjustsStack:    true
 registers:
   - { id: 0, class: gpr32, preferred-register: '' }
   - { id: 1, class: gpr32, preferred-register: '' }

llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir

@@ -116,7 +116,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    0
-  adjustsStack:    false
+  adjustsStack:    true
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295

llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir

@@ -114,7 +114,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    0
-  adjustsStack:    false
+  adjustsStack:    true
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295