Skip to content

Commit 7598502

Browse files
!fixup remove assert; rename test; only legal for rv32; remove fixme
1 parent aec060d commit 7598502

File tree

2 files changed

+7
-12
lines changed

2 files changed

+7
-12
lines changed

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -85,12 +85,13 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
8585
for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
8686
unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1;
8787
unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0;
88-
getActionDefinitionsBuilder(Op)
89-
.legalIf([=, &ST](const LegalityQuery &Query) -> bool {
90-
return ST.hasStdExtD() && typeIs(LitTyIdx, s32)(Query) &&
91-
typeIs(BigTyIdx, s64)(Query);
92-
})
93-
.widenScalarToNextPow2(LitTyIdx, XLen)
88+
auto &MergeUnmergeActions = getActionDefinitionsBuilder(Op);
89+
if (XLen == 32 && ST.hasStdExtD()) {
90+
LLT IdxZeroTy = G_MERGE_VALUES ? s64 : s32;
91+
LLT IdxOneTy = G_MERGE_VALUES ? s32 : s64;
92+
MergeUnmergeActions.legalFor({IdxZeroTy, IdxOneTy});
93+
}
94+
MergeUnmergeActions.widenScalarToNextPow2(LitTyIdx, XLen)
9495
.widenScalarToNextPow2(BigTyIdx, XLen)
9596
.clampScalar(LitTyIdx, sXLen, sXLen)
9697
.clampScalar(BigTyIdx, sXLen, sXLen);

llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -425,12 +425,9 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
425425
}
426426
case TargetOpcode::G_MERGE_VALUES: {
427427
// Use FPR64 for s64 merge on rv32.
428-
assert(MI.getNumOperands() == 3 && "Unsupported G_MERGE_VALUES");
429428
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
430429
if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
431430
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
432-
// FIXME: OpdsMapping[0, 1] should probably visit their uses to determine
433-
// if GPRValueMapping or FPRValueMapping
434431
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
435432
OpdsMapping[1] = GPRValueMapping;
436433
OpdsMapping[2] = GPRValueMapping;
@@ -439,12 +436,9 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
439436
}
440437
case TargetOpcode::G_UNMERGE_VALUES: {
441438
// Use FPR64 for s64 unmerge on rv32.
442-
assert(MI.getNumOperands() == 3 && "Unsupported G_UNMERGE_VALUES");
443439
LLT Ty = MRI.getType(MI.getOperand(2).getReg());
444440
if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
445441
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
446-
// FIXME: OpdsMapping[0, 1] should probably visit their uses to determine
447-
// if GPRValueMapping or FPRValueMapping
448442
OpdsMapping[0] = GPRValueMapping;
449443
OpdsMapping[1] = GPRValueMapping;
450444
OpdsMapping[2] = getFPValueMapping(Ty.getSizeInBits());

0 commit comments

Comments
 (0)