@@ -425,12 +425,9 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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}
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case TargetOpcode::G_MERGE_VALUES: {
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// Use FPR64 for s64 merge on rv32.
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- assert (MI.getNumOperands () == 3 && " Unsupported G_MERGE_VALUES" );
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LLT Ty = MRI.getType (MI.getOperand (0 ).getReg ());
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if (GPRSize == 32 && Ty.getSizeInBits () == 64 ) {
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assert (MF.getSubtarget <RISCVSubtarget>().hasStdExtD ());
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- // FIXME: OpdsMapping[0, 1] should probably visit their uses to determine
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- // if GPRValueMapping or FPRValueMapping
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OpdsMapping[0 ] = getFPValueMapping (Ty.getSizeInBits ());
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OpdsMapping[1 ] = GPRValueMapping;
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OpdsMapping[2 ] = GPRValueMapping;
@@ -439,12 +436,9 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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}
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case TargetOpcode::G_UNMERGE_VALUES: {
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// Use FPR64 for s64 unmerge on rv32.
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- assert (MI.getNumOperands () == 3 && " Unsupported G_UNMERGE_VALUES" );
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LLT Ty = MRI.getType (MI.getOperand (2 ).getReg ());
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if (GPRSize == 32 && Ty.getSizeInBits () == 64 ) {
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assert (MF.getSubtarget <RISCVSubtarget>().hasStdExtD ());
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- // FIXME: OpdsMapping[0, 1] should probably visit their uses to determine
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- // if GPRValueMapping or FPRValueMapping
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OpdsMapping[0 ] = GPRValueMapping;
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OpdsMapping[1 ] = GPRValueMapping;
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OpdsMapping[2 ] = getFPValueMapping (Ty.getSizeInBits ());
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