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[RISCV] Add back some test cases I inadvertently deleted. NFC
These tests were accidentally removed in a7a1195. I only meant to remove bfloat tests, but I accidentally removed f32 and f64 as well.
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll

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@@ -119,3 +119,227 @@ define <16 x half> @selectcc_v16f16(half %a, half %b, <16 x half> %c, <16 x half
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%v = select i1 %cmp, <16 x half> %c, <16 x half> %d
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ret <16 x half> %v
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}
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define <2 x float> @select_v2f32(i1 zeroext %c, <2 x float> %a, <2 x float> %b) {
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; CHECK-LABEL: select_v2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vmv.v.x v10, a0
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; CHECK-NEXT: vmsne.vi v0, v10, 0
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; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
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; CHECK-NEXT: ret
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%v = select i1 %c, <2 x float> %a, <2 x float> %b
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ret <2 x float> %v
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}
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define <2 x float> @selectcc_v2f32(float %a, float %b, <2 x float> %c, <2 x float> %d) {
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; CHECK-LABEL: selectcc_v2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: feq.s a0, fa0, fa1
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vmv.v.x v10, a0
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; CHECK-NEXT: vmsne.vi v0, v10, 0
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; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
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; CHECK-NEXT: ret
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%cmp = fcmp oeq float %a, %b
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%v = select i1 %cmp, <2 x float> %c, <2 x float> %d
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ret <2 x float> %v
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}
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define <4 x float> @select_v4f32(i1 zeroext %c, <4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: select_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.x v10, a0
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; CHECK-NEXT: vmsne.vi v0, v10, 0
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
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; CHECK-NEXT: ret
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%v = select i1 %c, <4 x float> %a, <4 x float> %b
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ret <4 x float> %v
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}
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define <4 x float> @selectcc_v4f32(float %a, float %b, <4 x float> %c, <4 x float> %d) {
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; CHECK-LABEL: selectcc_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: feq.s a0, fa0, fa1
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.x v10, a0
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; CHECK-NEXT: vmsne.vi v0, v10, 0
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
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; CHECK-NEXT: ret
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%cmp = fcmp oeq float %a, %b
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%v = select i1 %cmp, <4 x float> %c, <4 x float> %d
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ret <4 x float> %v
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}
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define <8 x float> @select_v8f32(i1 zeroext %c, <8 x float> %a, <8 x float> %b) {
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; CHECK-LABEL: select_v8f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmv.v.x v12, a0
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; CHECK-NEXT: vmsne.vi v0, v12, 0
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
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; CHECK-NEXT: ret
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%v = select i1 %c, <8 x float> %a, <8 x float> %b
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ret <8 x float> %v
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}
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define <8 x float> @selectcc_v8f32(float %a, float %b, <8 x float> %c, <8 x float> %d) {
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; CHECK-LABEL: selectcc_v8f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: feq.s a0, fa0, fa1
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmv.v.x v12, a0
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; CHECK-NEXT: vmsne.vi v0, v12, 0
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
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; CHECK-NEXT: ret
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%cmp = fcmp oeq float %a, %b
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%v = select i1 %cmp, <8 x float> %c, <8 x float> %d
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ret <8 x float> %v
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}
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define <16 x float> @select_v16f32(i1 zeroext %c, <16 x float> %a, <16 x float> %b) {
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; CHECK-LABEL: select_v16f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmv.v.x v16, a0
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; CHECK-NEXT: vmsne.vi v0, v16, 0
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
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; CHECK-NEXT: ret
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%v = select i1 %c, <16 x float> %a, <16 x float> %b
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ret <16 x float> %v
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}
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define <16 x float> @selectcc_v16f32(float %a, float %b, <16 x float> %c, <16 x float> %d) {
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; CHECK-LABEL: selectcc_v16f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: feq.s a0, fa0, fa1
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmv.v.x v16, a0
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; CHECK-NEXT: vmsne.vi v0, v16, 0
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
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; CHECK-NEXT: ret
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%cmp = fcmp oeq float %a, %b
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%v = select i1 %cmp, <16 x float> %c, <16 x float> %d
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ret <16 x float> %v
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}
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define <2 x double> @select_v2f64(i1 zeroext %c, <2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: select_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vmv.v.x v10, a0
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; CHECK-NEXT: vmsne.vi v0, v10, 0
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; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
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; CHECK-NEXT: ret
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%v = select i1 %c, <2 x double> %a, <2 x double> %b
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ret <2 x double> %v
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}
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define <2 x double> @selectcc_v2f64(double %a, double %b, <2 x double> %c, <2 x double> %d) {
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; CHECK-LABEL: selectcc_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: feq.d a0, fa0, fa1
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vmv.v.x v10, a0
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; CHECK-NEXT: vmsne.vi v0, v10, 0
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; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
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; CHECK-NEXT: ret
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%cmp = fcmp oeq double %a, %b
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%v = select i1 %cmp, <2 x double> %c, <2 x double> %d
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ret <2 x double> %v
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}
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define <4 x double> @select_v4f64(i1 zeroext %c, <4 x double> %a, <4 x double> %b) {
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; CHECK-LABEL: select_v4f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.x v12, a0
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; CHECK-NEXT: vmsne.vi v0, v12, 0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
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; CHECK-NEXT: ret
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%v = select i1 %c, <4 x double> %a, <4 x double> %b
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ret <4 x double> %v
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}
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define <4 x double> @selectcc_v4f64(double %a, double %b, <4 x double> %c, <4 x double> %d) {
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; CHECK-LABEL: selectcc_v4f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: feq.d a0, fa0, fa1
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.x v12, a0
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; CHECK-NEXT: vmsne.vi v0, v12, 0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
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; CHECK-NEXT: ret
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%cmp = fcmp oeq double %a, %b
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%v = select i1 %cmp, <4 x double> %c, <4 x double> %d
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ret <4 x double> %v
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}
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define <8 x double> @select_v8f64(i1 zeroext %c, <8 x double> %a, <8 x double> %b) {
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; CHECK-LABEL: select_v8f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmv.v.x v16, a0
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; CHECK-NEXT: vmsne.vi v0, v16, 0
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; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
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; CHECK-NEXT: ret
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%v = select i1 %c, <8 x double> %a, <8 x double> %b
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ret <8 x double> %v
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}
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define <8 x double> @selectcc_v8f64(double %a, double %b, <8 x double> %c, <8 x double> %d) {
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; CHECK-LABEL: selectcc_v8f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: feq.d a0, fa0, fa1
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmv.v.x v16, a0
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; CHECK-NEXT: vmsne.vi v0, v16, 0
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; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
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; CHECK-NEXT: ret
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%cmp = fcmp oeq double %a, %b
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%v = select i1 %cmp, <8 x double> %c, <8 x double> %d
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ret <8 x double> %v
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}
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define <16 x double> @select_v16f64(i1 zeroext %c, <16 x double> %a, <16 x double> %b) {
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; CHECK-LABEL: select_v16f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmv.v.x v24, a0
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; CHECK-NEXT: vmsne.vi v0, v24, 0
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; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
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; CHECK-NEXT: ret
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%v = select i1 %c, <16 x double> %a, <16 x double> %b
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ret <16 x double> %v
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}
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define <16 x double> @selectcc_v16f64(double %a, double %b, <16 x double> %c, <16 x double> %d) {
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; CHECK-LABEL: selectcc_v16f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: feq.d a0, fa0, fa1
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmv.v.x v24, a0
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; CHECK-NEXT: vmsne.vi v0, v24, 0
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; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
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; CHECK-NEXT: ret
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%cmp = fcmp oeq double %a, %b
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%v = select i1 %cmp, <16 x double> %c, <16 x double> %d
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ret <16 x double> %v
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}

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