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Implement reviewer suggestions
1 parent fd680df commit 760e22e

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2 files changed

+17
-20
lines changed

2 files changed

+17
-20
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2650,7 +2650,7 @@ SDValue DAGCombiner::visitPTRADD(SDNode *N) {
26502650
return N0;
26512651

26522652
// fold (ptradd 0, x) -> x
2653-
if (isNullConstant(N0) && PtrVT == IntVT)
2653+
if (PtrVT == IntVT && isNullConstant(N0))
26542654
return N1;
26552655

26562656
if (N0.getOpcode() != ISD::PTRADD ||
@@ -2668,10 +2668,9 @@ SDValue DAGCombiner::visitPTRADD(SDNode *N) {
26682668
// * y is a constant and (ptradd x, y) has one use; or
26692669
// * y and z are both constants.
26702670
if ((YIsConstant && N0OneUse) || (YIsConstant && ZIsConstant)) {
2671-
SDNodeFlags Flags;
26722671
// If both additions in the original were NUW, the new ones are as well.
2673-
if (N->getFlags().hasNoUnsignedWrap() && N0->getFlags().hasNoUnsignedWrap())
2674-
Flags |= SDNodeFlags::NoUnsignedWrap;
2672+
SDNodeFlags Flags =
2673+
(N->getFlags() & N0->getFlags()) & SDNodeFlags::NoUnsignedWrap;
26752674
SDValue Add = DAG.getNode(ISD::ADD, DL, IntVT, {Y, Z}, Flags);
26762675
AddToWorklist(Add.getNode());
26772676
return DAG.getMemBasePlusOffset(X, Add, DL, Flags);

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 14 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -14968,22 +14968,20 @@ SDValue SITargetLowering::performPtrAddCombine(SDNode *N,
1496814968
SDValue X = N0;
1496914969
SDValue Y = N1.getOperand(0);
1497014970
SDValue Z = N1.getOperand(1);
14971-
bool N1OneUse = N1.hasOneUse();
14972-
bool YIsConstant = DAG.isConstantIntBuildVectorOrConstantInt(Y);
14973-
bool ZIsConstant = DAG.isConstantIntBuildVectorOrConstantInt(Z);
14974-
if ((ZIsConstant != YIsConstant) && N1OneUse) {
14975-
SDNodeFlags Flags;
14976-
// If both additions in the original were NUW, the new ones are as well.
14977-
if (N->getFlags().hasNoUnsignedWrap() &&
14978-
N1->getFlags().hasNoUnsignedWrap())
14979-
Flags |= SDNodeFlags::NoUnsignedWrap;
14980-
14981-
if (YIsConstant)
14982-
std::swap(Y, Z);
14983-
14984-
SDValue Inner = DAG.getMemBasePlusOffset(X, Y, DL, Flags);
14985-
DCI.AddToWorklist(Inner.getNode());
14986-
return DAG.getMemBasePlusOffset(Inner, Z, DL, Flags);
14971+
if (N1.hasOneUse()) {
14972+
bool YIsConstant = DAG.isConstantIntBuildVectorOrConstantInt(Y);
14973+
bool ZIsConstant = DAG.isConstantIntBuildVectorOrConstantInt(Z);
14974+
if (ZIsConstant != YIsConstant) {
14975+
// If both additions in the original were NUW, the new ones are as well.
14976+
SDNodeFlags Flags =
14977+
(N->getFlags() & N1->getFlags()) & SDNodeFlags::NoUnsignedWrap;
14978+
if (YIsConstant)
14979+
std::swap(Y, Z);
14980+
14981+
SDValue Inner = DAG.getMemBasePlusOffset(X, Y, DL, Flags);
14982+
DCI.AddToWorklist(Inner.getNode());
14983+
return DAG.getMemBasePlusOffset(Inner, Z, DL, Flags);
14984+
}
1498714985
}
1498814986
}
1498914987

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