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arsenmarsenm
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R600: Make ShaderType private
llvm-svn: 212896
1 parent 7d5e2cb commit 762af96

9 files changed

+45
-34
lines changed

‎llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,6 @@
1616
//===----------------------------------------------------------------------===//
1717
//
1818

19-
2019
#include "AMDGPUAsmPrinter.h"
2120
#include "AMDGPU.h"
2221
#include "AMDGPUSubtarget.h"
@@ -179,7 +178,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
179178
unsigned RsrcReg;
180179
if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
181180
// Evergreen / Northern Islands
182-
switch (MFI->ShaderType) {
181+
switch (MFI->getShaderType()) {
183182
default: // Fall through
184183
case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
185184
case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
@@ -188,7 +187,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
188187
}
189188
} else {
190189
// R600 / R700
191-
switch (MFI->ShaderType) {
190+
switch (MFI->getShaderType()) {
192191
default: // Fall through
193192
case ShaderType::GEOMETRY: // Fall through
194193
case ShaderType::COMPUTE: // Fall through
@@ -203,7 +202,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
203202
OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
204203
OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
205204

206-
if (MFI->ShaderType == ShaderType::COMPUTE) {
205+
if (MFI->getShaderType() == ShaderType::COMPUTE) {
207206
OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
208207
OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
209208
}
@@ -324,7 +323,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF,
324323
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
325324

326325
unsigned RsrcReg;
327-
switch (MFI->ShaderType) {
326+
switch (MFI->getShaderType()) {
328327
default: // Fall through
329328
case ShaderType::COMPUTE: RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
330329
case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
@@ -344,7 +343,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF,
344343
unsigned LDSBlocks =
345344
RoundUpToAlignment(MFI->LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
346345

347-
if (MFI->ShaderType == ShaderType::COMPUTE) {
346+
if (MFI->getShaderType() == ShaderType::COMPUTE) {
348347
OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
349348

350349
const uint32_t ComputePGMRSrc1 =
@@ -367,7 +366,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF,
367366
S_00B028_SGPRS(KernelInfo.NumSGPR / 8), 4);
368367
}
369368

370-
if (MFI->ShaderType == ShaderType::PIXEL) {
369+
if (MFI->getShaderType() == ShaderType::PIXEL) {
371370
OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
372371
OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(LDSBlocks), 4);
373372
OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);

‎llvm/lib/Target/R600/AMDGPUCallingConv.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -62,11 +62,11 @@ def CC_AMDGPU : CallingConv<[
6262
CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>().getGeneration() >= "
6363
"AMDGPUSubtarget::SOUTHERN_ISLANDS && "
6464
"State.getMachineFunction().getInfo<SIMachineFunctionInfo>()->"#
65-
"ShaderType == ShaderType::COMPUTE", CCDelegateTo<CC_AMDGPU_Kernel>>,
65+
"getShaderType() == ShaderType::COMPUTE", CCDelegateTo<CC_AMDGPU_Kernel>>,
6666
CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>().getGeneration() < "
6767
"AMDGPUSubtarget::SOUTHERN_ISLANDS && "
6868
"State.getMachineFunction().getInfo<R600MachineFunctionInfo>()->"
69-
"ShaderType == ShaderType::COMPUTE", CCDelegateTo<CC_AMDGPU_Kernel>>,
69+
"getShaderType() == ShaderType::COMPUTE", CCDelegateTo<CC_AMDGPU_Kernel>>,
7070
CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>()"#
7171
".getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS", CCDelegateTo<CC_SI>>,
7272
CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>()"#

‎llvm/lib/Target/R600/AMDGPUMachineFunction.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,9 +10,9 @@ static const char *const ShaderTypeAttribute = "ShaderType";
1010
void AMDGPUMachineFunction::anchor() {}
1111

1212
AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF) :
13-
MachineFunctionInfo() {
14-
ShaderType = ShaderType::COMPUTE;
15-
LDSSize = 0;
13+
MachineFunctionInfo(),
14+
ShaderType(ShaderType::COMPUTE),
15+
LDSSize(0) {
1616
AttributeSet Set = MF.getFunction()->getAttributes();
1717
Attribute A = Set.getAttribute(AttributeSet::FunctionIndex,
1818
ShaderTypeAttribute);

‎llvm/lib/Target/R600/AMDGPUMachineFunction.h

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,14 +20,19 @@ namespace llvm {
2020

2121
class AMDGPUMachineFunction : public MachineFunctionInfo {
2222
virtual void anchor();
23+
unsigned ShaderType;
24+
2325
public:
2426
AMDGPUMachineFunction(const MachineFunction &MF);
25-
unsigned ShaderType;
2627
/// A map to keep track of local memory objects and their offsets within
2728
/// the local memory space.
2829
std::map<const GlobalValue *, unsigned> LocalMemoryObjects;
2930
/// Number of bytes in the LDS that are being used.
3031
unsigned LDSSize;
32+
33+
unsigned getShaderType() const {
34+
return ShaderType;
35+
}
3136
};
3237

3338
}

‎llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -481,14 +481,14 @@ class R600ControlFlowFinalizer : public MachineFunctionPass {
481481
TRI=static_cast<const R600RegisterInfo *>(MF.getTarget().getRegisterInfo());
482482
R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
483483

484-
CFStack CFStack(ST, MFI->ShaderType);
484+
CFStack CFStack(ST, MFI->getShaderType());
485485
for (MachineFunction::iterator MB = MF.begin(), ME = MF.end(); MB != ME;
486486
++MB) {
487487
MachineBasicBlock &MBB = *MB;
488488
unsigned CfCount = 0;
489489
std::vector<std::pair<unsigned, std::set<MachineInstr *> > > LoopStack;
490490
std::vector<MachineInstr * > IfThenElseStack;
491-
if (MFI->ShaderType == 1) {
491+
if (MFI->getShaderType() == ShaderType::VERTEX) {
492492
BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
493493
getHWInstrDesc(CF_CALL_FS));
494494
CfCount++;

‎llvm/lib/Target/R600/R600ISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1680,7 +1680,7 @@ SDValue R600TargetLowering::LowerFormalArguments(
16801680
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
16811681
getTargetMachine(), ArgLocs, *DAG.getContext());
16821682
MachineFunction &MF = DAG.getMachineFunction();
1683-
unsigned ShaderType = MF.getInfo<R600MachineFunctionInfo>()->ShaderType;
1683+
unsigned ShaderType = MF.getInfo<R600MachineFunctionInfo>()->getShaderType();
16841684

16851685
SmallVector<ISD::InputArg, 8> LocalIns;
16861686

‎llvm/lib/Target/R600/R600InstrInfo.cpp

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -209,18 +209,22 @@ bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
209209
}
210210

211211
bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
212-
const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
213-
return MFI->ShaderType != ShaderType::COMPUTE && usesVertexCache(MI->getOpcode());
212+
const MachineFunction *MF = MI->getParent()->getParent();
213+
const R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
214+
return MFI->getShaderType() != ShaderType::COMPUTE &&
215+
usesVertexCache(MI->getOpcode());
214216
}
215217

216218
bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
217219
return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
218220
}
219221

220222
bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
221-
const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
222-
return (MFI->ShaderType == ShaderType::COMPUTE && usesVertexCache(MI->getOpcode())) ||
223-
usesTextureCache(MI->getOpcode());
223+
const MachineFunction *MF = MI->getParent()->getParent();
224+
const R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
225+
return (MFI->getShaderType() == ShaderType::COMPUTE &&
226+
usesVertexCache(MI->getOpcode())) ||
227+
usesTextureCache(MI->getOpcode());
224228
}
225229

226230
bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {

‎llvm/lib/Target/R600/SIISelLowering.cpp

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -327,7 +327,7 @@ SDValue SITargetLowering::LowerFormalArguments(
327327
const ISD::InputArg &Arg = Ins[i];
328328

329329
// First check if it's a PS input addr
330-
if (Info->ShaderType == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
330+
if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
331331
!Arg.Flags.isByVal()) {
332332

333333
assert((PSInputNum <= 15) && "Too many PS inputs!");
@@ -343,7 +343,7 @@ SDValue SITargetLowering::LowerFormalArguments(
343343
}
344344

345345
// Second split vertices into their elements
346-
if (Info->ShaderType != ShaderType::COMPUTE && Arg.VT.isVector()) {
346+
if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
347347
ISD::InputArg NewArg = Arg;
348348
NewArg.Flags.setSplit();
349349
NewArg.VT = Arg.VT.getVectorElementType();
@@ -359,7 +359,7 @@ SDValue SITargetLowering::LowerFormalArguments(
359359
NewArg.PartOffset += NewArg.VT.getStoreSize();
360360
}
361361

362-
} else if (Info->ShaderType != ShaderType::COMPUTE) {
362+
} else if (Info->getShaderType() != ShaderType::COMPUTE) {
363363
Splits.push_back(Arg);
364364
}
365365
}
@@ -369,20 +369,21 @@ SDValue SITargetLowering::LowerFormalArguments(
369369
getTargetMachine(), ArgLocs, *DAG.getContext());
370370

371371
// At least one interpolation mode must be enabled or else the GPU will hang.
372-
if (Info->ShaderType == ShaderType::PIXEL && (Info->PSInputAddr & 0x7F) == 0) {
372+
if (Info->getShaderType() == ShaderType::PIXEL &&
373+
(Info->PSInputAddr & 0x7F) == 0) {
373374
Info->PSInputAddr |= 1;
374375
CCInfo.AllocateReg(AMDGPU::VGPR0);
375376
CCInfo.AllocateReg(AMDGPU::VGPR1);
376377
}
377378

378379
// The pointer to the list of arguments is stored in SGPR0, SGPR1
379-
if (Info->ShaderType == ShaderType::COMPUTE) {
380+
if (Info->getShaderType() == ShaderType::COMPUTE) {
380381
CCInfo.AllocateReg(AMDGPU::SGPR0);
381382
CCInfo.AllocateReg(AMDGPU::SGPR1);
382383
MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
383384
}
384385

385-
if (Info->ShaderType == ShaderType::COMPUTE) {
386+
if (Info->getShaderType() == ShaderType::COMPUTE) {
386387
getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
387388
Splits);
388389
}

‎llvm/lib/Target/R600/SILowerControlFlow.cpp

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -147,7 +147,7 @@ void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
147147
MachineBasicBlock &MBB = *MI.getParent();
148148
DebugLoc DL = MI.getDebugLoc();
149149

150-
if (MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType !=
150+
if (MBB.getParent()->getInfo<SIMachineFunctionInfo>()->getShaderType() !=
151151
ShaderType::PIXEL ||
152152
!shouldSkip(&MBB, &MBB.getParent()->back()))
153153
return;
@@ -298,11 +298,13 @@ void SILowerControlFlowPass::Kill(MachineInstr &MI) {
298298
DebugLoc DL = MI.getDebugLoc();
299299
const MachineOperand &Op = MI.getOperand(0);
300300

301-
// Kill is only allowed in pixel / geometry shaders
302-
assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
303-
ShaderType::PIXEL ||
304-
MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
305-
ShaderType::GEOMETRY);
301+
#ifndef NDEBUG
302+
const SIMachineFunctionInfo *MFI
303+
= MBB.getParent()->getInfo<SIMachineFunctionInfo>();
304+
// Kill is only allowed in pixel / geometry shaders.
305+
assert(MFI->getShaderType() == ShaderType::PIXEL ||
306+
MFI->getShaderType() == ShaderType::GEOMETRY);
307+
#endif
306308

307309
// Clear this thread from the exec mask if the operand is negative
308310
if ((Op.isImm() || Op.isFPImm())) {
@@ -540,7 +542,7 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
540542
InitM0ForLDS(MBB.getFirstNonPHI());
541543
}
542544

543-
if (NeedWQM && MFI->ShaderType == ShaderType::PIXEL) {
545+
if (NeedWQM && MFI->getShaderType() == ShaderType::PIXEL) {
544546
MachineBasicBlock &MBB = MF.front();
545547
BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
546548
AMDGPU::EXEC).addReg(AMDGPU::EXEC);

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