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[SLSR] Regenerate test checks (NFC)
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3 files changed

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‎llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/reassociate-geps-and-slsr-addrspace.ll

Lines changed: 56 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,24 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
12
; RUN: opt -S -mtriple=amdgcn-- -passes=separate-const-offset-from-gep,slsr,gvn < %s | FileCheck %s
2-
; RUN: opt -S -mtriple=amdgcn-- -passes="separate-const-offset-from-gep,slsr,gvn" < %s | FileCheck %s
33

44
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
55

66

7-
; CHECK-LABEL: @slsr_after_reassociate_global_geps_mubuf_max_offset(
8-
; CHECK: [[b1:%[0-9]+]] = getelementptr float, ptr addrspace(1) %arr, i64 [[bump:%[0-9]+]]
9-
; CHECK: [[b2:%[0-9]+]] = getelementptr float, ptr addrspace(1) [[b1]], i64 [[bump]]
107
define amdgpu_kernel void @slsr_after_reassociate_global_geps_mubuf_max_offset(ptr addrspace(1) %out, ptr addrspace(1) noalias %arr, i32 %i) {
8+
; CHECK-LABEL: define amdgpu_kernel void @slsr_after_reassociate_global_geps_mubuf_max_offset(
9+
; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) noalias [[ARR:%.*]], i32 [[I:%.*]]) {
10+
; CHECK-NEXT: bb:
11+
; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[I]] to i64
12+
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, ptr addrspace(1) [[ARR]], i64 [[TMP0]]
13+
; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[TMP1]], i64 1023
14+
; CHECK-NEXT: [[V11:%.*]] = load i32, ptr addrspace(1) [[P12]], align 4
15+
; CHECK-NEXT: store i32 [[V11]], ptr addrspace(1) [[OUT]], align 4
16+
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr float, ptr addrspace(1) [[TMP1]], i64 [[TMP0]]
17+
; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[TMP2]], i64 1023
18+
; CHECK-NEXT: [[V22:%.*]] = load i32, ptr addrspace(1) [[P24]], align 4
19+
; CHECK-NEXT: store i32 [[V22]], ptr addrspace(1) [[OUT]], align 4
20+
; CHECK-NEXT: ret void
21+
;
1122
bb:
1223
%i2 = shl nsw i32 %i, 1
1324
%j1 = add nsw i32 %i, 1023
@@ -25,12 +36,22 @@ bb:
2536
ret void
2637
}
2738

28-
; CHECK-LABEL: @slsr_after_reassociate_global_geps_over_mubuf_max_offset(
29-
; CHECK: %j1 = add nsw i32 %i, 1024
30-
; CHECK: %tmp = sext i32 %j1 to i64
31-
; CHECK: getelementptr inbounds float, ptr addrspace(1) %arr, i64 %tmp
32-
; CHECK: getelementptr inbounds float, ptr addrspace(1) %arr, i64 %tmp5
3339
define amdgpu_kernel void @slsr_after_reassociate_global_geps_over_mubuf_max_offset(ptr addrspace(1) %out, ptr addrspace(1) noalias %arr, i32 %i) {
40+
; CHECK-LABEL: define amdgpu_kernel void @slsr_after_reassociate_global_geps_over_mubuf_max_offset(
41+
; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(1) noalias [[ARR:%.*]], i32 [[I:%.*]]) {
42+
; CHECK-NEXT: bb:
43+
; CHECK-NEXT: [[J1:%.*]] = add nsw i32 [[I]], 1024
44+
; CHECK-NEXT: [[TMP:%.*]] = sext i32 [[J1]] to i64
45+
; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[ARR]], i64 [[TMP]]
46+
; CHECK-NEXT: [[V11:%.*]] = load i32, ptr addrspace(1) [[P1]], align 4
47+
; CHECK-NEXT: store i32 [[V11]], ptr addrspace(1) [[OUT]], align 4
48+
; CHECK-NEXT: [[J2:%.*]] = add i32 [[J1]], [[I]]
49+
; CHECK-NEXT: [[TMP5:%.*]] = sext i32 [[J2]] to i64
50+
; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[ARR]], i64 [[TMP5]]
51+
; CHECK-NEXT: [[V22:%.*]] = load i32, ptr addrspace(1) [[P2]], align 4
52+
; CHECK-NEXT: store i32 [[V22]], ptr addrspace(1) [[OUT]], align 4
53+
; CHECK-NEXT: ret void
54+
;
3455
bb:
3556
%i2 = shl nsw i32 %i, 1
3657
%j1 = add nsw i32 %i, 1024
@@ -48,13 +69,21 @@ bb:
4869
ret void
4970
}
5071

51-
; CHECK-LABEL: @slsr_after_reassociate_lds_geps_ds_max_offset(
52-
; CHECK: [[B1:%[0-9]+]] = getelementptr float, ptr addrspace(3) %arr, i32 %i
53-
; CHECK: getelementptr inbounds float, ptr addrspace(3) [[B1]], i32 16383
5472

55-
; CHECK: [[B2:%[0-9]+]] = getelementptr float, ptr addrspace(3) [[B1]], i32 %i
56-
; CHECK: getelementptr inbounds float, ptr addrspace(3) [[B2]], i32 16383
5773
define amdgpu_kernel void @slsr_after_reassociate_lds_geps_ds_max_offset(ptr addrspace(1) %out, ptr addrspace(3) noalias %arr, i32 %i) {
74+
; CHECK-LABEL: define amdgpu_kernel void @slsr_after_reassociate_lds_geps_ds_max_offset(
75+
; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(3) noalias [[ARR:%.*]], i32 [[I:%.*]]) {
76+
; CHECK-NEXT: bb:
77+
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr float, ptr addrspace(3) [[ARR]], i32 [[I]]
78+
; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP0]], i32 16383
79+
; CHECK-NEXT: [[V11:%.*]] = load i32, ptr addrspace(3) [[P12]], align 4
80+
; CHECK-NEXT: store i32 [[V11]], ptr addrspace(1) [[OUT]], align 4
81+
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, ptr addrspace(3) [[TMP0]], i32 [[I]]
82+
; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[TMP1]], i32 16383
83+
; CHECK-NEXT: [[V22:%.*]] = load i32, ptr addrspace(3) [[P24]], align 4
84+
; CHECK-NEXT: store i32 [[V22]], ptr addrspace(1) [[OUT]], align 4
85+
; CHECK-NEXT: ret void
86+
;
5887
bb:
5988
%i2 = shl nsw i32 %i, 1
6089
%j1 = add nsw i32 %i, 16383
@@ -70,12 +99,20 @@ bb:
7099
ret void
71100
}
72101

73-
; CHECK-LABEL: @slsr_after_reassociate_lds_geps_over_ds_max_offset(
74-
; CHECK: %j1 = add nsw i32 %i, 16384
75-
; CHECK: getelementptr inbounds float, ptr addrspace(3) %arr, i32 %j1
76-
; CHECK: %j2 = add i32 %j1, %i
77-
; CHECK: getelementptr inbounds float, ptr addrspace(3) %arr, i32 %j2
78102
define amdgpu_kernel void @slsr_after_reassociate_lds_geps_over_ds_max_offset(ptr addrspace(1) %out, ptr addrspace(3) noalias %arr, i32 %i) {
103+
; CHECK-LABEL: define amdgpu_kernel void @slsr_after_reassociate_lds_geps_over_ds_max_offset(
104+
; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(3) noalias [[ARR:%.*]], i32 [[I:%.*]]) {
105+
; CHECK-NEXT: bb:
106+
; CHECK-NEXT: [[J1:%.*]] = add nsw i32 [[I]], 16384
107+
; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[ARR]], i32 [[J1]]
108+
; CHECK-NEXT: [[V11:%.*]] = load i32, ptr addrspace(3) [[P1]], align 4
109+
; CHECK-NEXT: store i32 [[V11]], ptr addrspace(1) [[OUT]], align 4
110+
; CHECK-NEXT: [[J2:%.*]] = add i32 [[J1]], [[I]]
111+
; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds float, ptr addrspace(3) [[ARR]], i32 [[J2]]
112+
; CHECK-NEXT: [[V22:%.*]] = load i32, ptr addrspace(3) [[P2]], align 4
113+
; CHECK-NEXT: store i32 [[V22]], ptr addrspace(1) [[OUT]], align 4
114+
; CHECK-NEXT: ret void
115+
;
79116
bb:
80117
%i2 = shl nsw i32 %i, 1
81118
%j1 = add nsw i32 %i, 16384

‎llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll

Lines changed: 22 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
12
; RUN: opt < %s -passes=separate-const-offset-from-gep,slsr,gvn -S | FileCheck %s
23
; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s --check-prefix=PTX
3-
; RUN: opt < %s -passes="separate-const-offset-from-gep,slsr,gvn" -S | FileCheck %s
44

55
target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
66
target triple = "nvptx64-unknown-unknown"
@@ -28,7 +28,27 @@ target triple = "nvptx64-unknown-unknown"
2828
; p4 = p3 + i
2929
; *(p4 + 5)
3030
define void @slsr_after_reassociate_geps(ptr %arr, i32 %i) {
31-
; CHECK-LABEL: @slsr_after_reassociate_geps(
31+
; CHECK-LABEL: define void @slsr_after_reassociate_geps(
32+
; CHECK-SAME: ptr [[ARR:%.*]], i32 [[I:%.*]]) {
33+
; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[I]] to i64
34+
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr float, ptr [[ARR]], i64 [[TMP1]]
35+
; CHECK-NEXT: [[P12:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 5
36+
; CHECK-NEXT: [[V1:%.*]] = load float, ptr [[P12]], align 4
37+
; CHECK-NEXT: call void @foo(float [[V1]])
38+
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr float, ptr [[TMP2]], i64 [[TMP1]]
39+
; CHECK-NEXT: [[P24:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i64 5
40+
; CHECK-NEXT: [[V2:%.*]] = load float, ptr [[P24]], align 4
41+
; CHECK-NEXT: call void @foo(float [[V2]])
42+
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr float, ptr [[TMP3]], i64 [[TMP1]]
43+
; CHECK-NEXT: [[P36:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 5
44+
; CHECK-NEXT: [[V3:%.*]] = load float, ptr [[P36]], align 4
45+
; CHECK-NEXT: call void @foo(float [[V3]])
46+
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[TMP4]], i64 [[TMP1]]
47+
; CHECK-NEXT: [[P48:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 5
48+
; CHECK-NEXT: [[V4:%.*]] = load float, ptr [[P48]], align 4
49+
; CHECK-NEXT: call void @foo(float [[V4]])
50+
; CHECK-NEXT: ret void
51+
;
3252
; PTX-LABEL: .visible .func slsr_after_reassociate_geps(
3353
; PTX: ld.param.u64 [[arr:%rd[0-9]+]], [slsr_after_reassociate_geps_param_0];
3454
; PTX: ld.param.u32 [[i:%r[0-9]+]], [slsr_after_reassociate_geps_param_1];
@@ -38,7 +58,6 @@ define void @slsr_after_reassociate_geps(ptr %arr, i32 %i) {
3858

3959
%j1 = add nsw i32 %i, 5
4060
%p1 = getelementptr inbounds float, ptr %arr, i32 %j1
41-
; CHECK: [[b1:%[0-9]+]] = getelementptr float, ptr %arr, i64 [[bump:%[0-9]+]]
4261
; PTX: mul.wide.s32 [[i4:%rd[0-9]+]], [[i]], 4;
4362
; PTX: add.s64 [[base1:%rd[0-9]+]], [[arr]], [[i4]];
4463
%v1 = load float, ptr %p1, align 4
@@ -47,23 +66,20 @@ define void @slsr_after_reassociate_geps(ptr %arr, i32 %i) {
4766

4867
%j2 = add nsw i32 %i2, 5
4968
%p2 = getelementptr inbounds float, ptr %arr, i32 %j2
50-
; CHECK: [[b2:%[0-9]+]] = getelementptr float, ptr [[b1]], i64 [[bump]]
5169
; PTX: add.s64 [[base2:%rd[0-9]+]], [[base1]], [[i4]];
5270
%v2 = load float, ptr %p2, align 4
5371
; PTX: ld.f32 {{%f[0-9]+}}, [[[base2]]+20];
5472
call void @foo(float %v2)
5573

5674
%j3 = add nsw i32 %i3, 5
5775
%p3 = getelementptr inbounds float, ptr %arr, i32 %j3
58-
; CHECK: [[b3:%[0-9]+]] = getelementptr float, ptr [[b2]], i64 [[bump]]
5976
; PTX: add.s64 [[base3:%rd[0-9]+]], [[base2]], [[i4]];
6077
%v3 = load float, ptr %p3, align 4
6178
; PTX: ld.f32 {{%f[0-9]+}}, [[[base3]]+20];
6279
call void @foo(float %v3)
6380

6481
%j4 = add nsw i32 %i4, 5
6582
%p4 = getelementptr inbounds float, ptr %arr, i32 %j4
66-
; CHECK: [[b4:%[0-9]+]] = getelementptr float, ptr [[b3]], i64 [[bump]]
6783
; PTX: add.s64 [[base4:%rd[0-9]+]], [[base3]], [[i4]];
6884
%v4 = load float, ptr %p4, align 4
6985
; PTX: ld.f32 {{%f[0-9]+}}, [[[base4]]+20];

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