[DAG] combineShiftToAVG - don't create avgfloor with scalar constant operands unless legal.

Converting to avgfloor and then expanding it back to shift+add later is likely to prevent other folds (re-association and value-tracking in particular) in the meantime.

Fixes #95284

Author: RKSimon

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -1078,6 +1078,12 @@ static SDValue combineShiftToAVG(SDValue Op,
       return SDValue();
   }
 
+  // Don't create a AVGFLOOR node with a scalar constant unless its legal as
+  // this is likely to stop other folds (reassociation, value tracking etc.)
+  if (!IsCeil && !TLI.isOperationLegal(AVGOpc, NVT) &&
+      (isa<ConstantSDNode>(ExtOpA) || isa<ConstantSDNode>(ExtOpB)))
+    return SDValue();
+
   SDLoc DL(Op);
   SDValue ResultAVG =
       DAG.getNode(AVGOpc, DL, NVT, DAG.getExtOrTrunc(IsSigned, ExtOpA, DL, NVT),

llvm/test/CodeGen/RISCV/pr95284.ll

@@ -6,27 +6,27 @@
 define signext i64 @PR95284(i32 signext %0) {
 ; RV32I-LABEL: PR95284:
 ; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    addi a1, a0, -1
-; RV32I-NEXT:    srli a1, a1, 1
-; RV32I-NEXT:    seqz a0, a0
-; RV32I-NEXT:    slli a2, a0, 31
-; RV32I-NEXT:    or a1, a2, a1
-; RV32I-NEXT:    addi a1, a1, 1
-; RV32I-NEXT:    seqz a2, a1
-; RV32I-NEXT:    sub a2, a2, a0
-; RV32I-NEXT:    andi a0, a1, -2
-; RV32I-NEXT:    slli a1, a2, 1
+; RV32I-NEXT:    seqz a1, a0
+; RV32I-NEXT:    neg a2, a1
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    srli a2, a2, 1
+; RV32I-NEXT:    srli a0, a0, 1
+; RV32I-NEXT:    slli a1, a1, 31
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    addi a0, a0, 1
+; RV32I-NEXT:    seqz a1, a0
+; RV32I-NEXT:    add a1, a2, a1
+; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    srli a1, a1, 1
+; RV32I-NEXT:    andi a0, a0, -2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: PR95284:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    addi a0, a0, 1
-; RV64I-NEXT:    li a1, -3
-; RV64I-NEXT:    srli a1, a1, 1
-; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    andi a0, a0, -2
 ; RV64I-NEXT:    ret
 entry:
   %1 = zext nneg i32 %0 to i64

llvm/test/CodeGen/X86/avg.ll

@@ -2201,12 +2201,11 @@ define <8 x i16> @PR52131_not_zext_with_constant(<8 x i32> %a) {
 define i64 @PR95284(i32 %a0) {
 ; CHECK-LABEL: PR95284:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl %edi, %ecx
-; CHECK-NEXT:    decq %rcx
-; CHECK-NEXT:    shrq %rcx
-; CHECK-NEXT:    incq %rcx
-; CHECK-NEXT:    movabsq $9223372036854775806, %rax # imm = 0x7FFFFFFFFFFFFFFE
-; CHECK-NEXT:    andq %rcx, %rax
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    decq %rax
+; CHECK-NEXT:    shrq %rax
+; CHECK-NEXT:    incq %rax
+; CHECK-NEXT:    andq $-2, %rax
 ; CHECK-NEXT:    retq
   %ext = zext nneg i32 %a0 to i64
   %dec = add i64 %ext, -1