Revert "[PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel."

This reverts commit 2de74e1.

A test-suite failure occurs due to this commit, will fix soon.

Author: esmeyi

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

@@ -1197,60 +1197,6 @@ bool PPCMIPeephole::simplifyCode() {
                       combineSEXTAndSHL(MI, ToErase);
         break;
       }
-      case PPC::ANDI_rec:
-      case PPC::ANDI8_rec:
-      case PPC::ANDIS_rec:
-      case PPC::ANDIS8_rec: {
-        Register TrueReg =
-            TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
-        if (!TrueReg.isVirtual() || !MRI->hasOneNonDBGUse(TrueReg))
-          break;
-
-        MachineInstr *SrcMI = MRI->getVRegDef(TrueReg);
-        if (!SrcMI)
-          break;
-
-        unsigned SrcOpCode = SrcMI->getOpcode();
-        if (SrcOpCode != PPC::RLDICL && SrcOpCode != PPC::RLDICR)
-          break;
-
-        uint64_t AndImm = MI.getOperand(2).getImm();
-        if (MI.getOpcode() == PPC::ANDIS_rec ||
-            MI.getOpcode() == PPC::ANDIS8_rec)
-          AndImm <<= 16;
-        uint64_t LZeroAndImm = llvm::countl_zero<uint64_t>(AndImm);
-        uint64_t RZeroAndImm = llvm::countr_zero<uint64_t>(AndImm);
-        uint64_t ImmSrc = SrcMI->getOperand(3).getImm();
-
-        // We can transfer `RLDICL/RLDICR + ANDI_rec/ANDIS_rec` to `ANDI_rec 0`
-        // if all bits to AND are already zero in the input.
-        bool PatternResultZero =
-            (SrcOpCode == PPC::RLDICL && (RZeroAndImm + ImmSrc > 63)) ||
-            (SrcOpCode == PPC::RLDICR && LZeroAndImm > ImmSrc);
-
-        // We can eliminate RLDICL/RLDICR if it's used to clear bits and all
-        // bits cleared will be ANDed with 0 by ANDI_rec/ANDIS_rec.
-        bool PatternRemoveRotate =
-            SrcMI->getOperand(2).getImm() == 0 &&
-            ((SrcOpCode == PPC::RLDICL && LZeroAndImm >= ImmSrc) ||
-             (SrcOpCode == PPC::RLDICR && (RZeroAndImm + ImmSrc > 63)));
-
-        if (!PatternResultZero && !PatternRemoveRotate)
-          break;
-
-        LLVM_DEBUG(dbgs() << "Combining pair: ");
-        LLVM_DEBUG(SrcMI->dump());
-        LLVM_DEBUG(MI.dump());
-        if (PatternResultZero)
-          MI.getOperand(2).setImm(0);
-        MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
-        addRegToUpdate(MI.getOperand(1).getReg());
-        LLVM_DEBUG(dbgs() << "To: ");
-        LLVM_DEBUG(MI.dump());
-        Simplified = true;
-        SrcMI->eraseFromParent();
-        break;
-      }
       case PPC::RLWINM:
       case PPC::RLWINM_rec:
       case PPC::RLWINM8:

llvm/test/CodeGen/PowerPC/fold-rot-and-peephole.mir

@@ -2204,7 +2204,8 @@ entry:
 define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) {
 ; CHECK-LABEL: getvelsl:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andi. r3, r5, 1
+; CHECK-NEXT:    clrldi r3, r5, 32
+; CHECK-NEXT:    andi. r3, r3, 1
 ; CHECK-NEXT:    sldi r3, r3, 3
 ; CHECK-NEXT:    lvsl v3, 0, r3
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
@@ -2224,6 +2225,7 @@ define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) {
 ;
 ; CHECK-AIX-LABEL: getvelsl:
 ; CHECK-AIX:       # %bb.0: # %entry
+; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    andi. 3, 3, 1
 ; CHECK-AIX-NEXT:    sldi 3, 3, 3
 ; CHECK-AIX-NEXT:    lvsl 3, 0, 3
@@ -2240,7 +2242,8 @@ entry:
 define i64 @getvelul(<2 x i64> %vul, i32 signext %i) {
 ; CHECK-LABEL: getvelul:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andi. r3, r5, 1
+; CHECK-NEXT:    clrldi r3, r5, 32
+; CHECK-NEXT:    andi. r3, r3, 1
 ; CHECK-NEXT:    sldi r3, r3, 3
 ; CHECK-NEXT:    lvsl v3, 0, r3
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
@@ -2260,6 +2263,7 @@ define i64 @getvelul(<2 x i64> %vul, i32 signext %i) {
 ;
 ; CHECK-AIX-LABEL: getvelul:
 ; CHECK-AIX:       # %bb.0: # %entry
+; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    andi. 3, 3, 1
 ; CHECK-AIX-NEXT:    sldi 3, 3, 3
 ; CHECK-AIX-NEXT:    lvsl 3, 0, 3
@@ -2457,7 +2461,8 @@ entry:
 define double @getveld(<2 x double> %vd, i32 signext %i) {
 ; CHECK-LABEL: getveld:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andi. r3, r5, 1
+; CHECK-NEXT:    clrldi r3, r5, 32
+; CHECK-NEXT:    andi. r3, r3, 1
 ; CHECK-NEXT:    sldi r3, r3, 3
 ; CHECK-NEXT:    lvsl v3, 0, r3
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
@@ -2479,6 +2484,7 @@ define double @getveld(<2 x double> %vd, i32 signext %i) {
 ;
 ; CHECK-AIX-LABEL: getveld:
 ; CHECK-AIX:       # %bb.0: # %entry
+; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    andi. 3, 3, 1
 ; CHECK-AIX-NEXT:    sldi 3, 3, 3
 ; CHECK-AIX-NEXT:    lvsl 3, 0, 3