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[lldb][AArch64][Linux] Correct name of FPCR field
It should be "RMode" as in "rounding mode" not "RMMode".
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-5
lines changed

3 files changed

+5
-5
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lldb/source/Plugins/Process/Utility/RegisterFlagsLinux_arm64.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ LinuxArm64RegisterFlags::DetectMTECtrlFields(uint64_t hwcap, uint64_t hwcap2) {
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LinuxArm64RegisterFlags::Fields
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LinuxArm64RegisterFlags::DetectFPCRFields(uint64_t hwcap, uint64_t hwcap2) {
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std::vector<RegisterFlags::Field> fpcr_fields{
56-
{"AHP", 26}, {"DN", 25}, {"FZ", 24}, {"RMMode", 22, 23},
56+
{"AHP", 26}, {"DN", 25}, {"FZ", 24}, {"RMode", 22, 23},
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// Bits 21-20 are "Stride" which is unused in AArch64 state.
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};
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lldb/test/API/commands/register/register/register_command/TestRegisters.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -630,9 +630,9 @@ def test_register_read_fields(self):
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# N/Z/C/V bits will always be present, so check only for those.
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self.expect("register read cpsr", substrs=["= (N = 0, Z = 1, C = 1, V = 0"])
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self.expect("register read fpsr", substrs=["= (QC = 0, IDC = 0, IXC = 0"])
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# AHP/DN/FZ/RMMode always present, others may vary.
633+
# AHP/DN/FZ/RMode always present, others may vary.
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self.expect(
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"register read fpcr", substrs=["= (AHP = 0, DN = 0, FZ = 0, RMMode = 0"]
635+
"register read fpcr", substrs=["= (AHP = 0, DN = 0, FZ = 0, RMode = 0"]
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)
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@skipUnlessPlatform(["linux"])

lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -578,9 +578,9 @@ def test_aarch64_sve_regs_full(self):
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# The N/Z/C/V bits are always present so just check for those.
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self.expect("register read cpsr", substrs=["= (N = 0, Z = 0, C = 0, V = 0"])
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self.expect("register read fpsr", substrs=["= (QC = 0, IDC = 0, IXC = 0"])
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# AHP/DN/FZ/RMMode always present, others may vary.
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# AHP/DN/FZ/RMode always present, others may vary.
582582
self.expect(
583-
"register read fpcr", substrs=["= (AHP = 0, DN = 0, FZ = 0, RMMode = 0"]
583+
"register read fpcr", substrs=["= (AHP = 0, DN = 0, FZ = 0, RMode = 0"]
584584
)
585585

586586
@skipIfLLVMTargetMissing("AArch64")

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