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davemgreendavemgreen
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[GlobalISel] Fix ZExt known bits for scalable vectors.
It was using the full size of the vector as the SrcBitWidth. This patch changes the code to split G_ASSERT_ZEXT away from the others (G_INTTOPTR / G_PTRTOINT / G_ZEXT / G_TRUNC) which are simpler, and make the code match the SDAG equivalent.
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4 files changed

+212
-16
lines changed

4 files changed

+212
-16
lines changed

‎llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp

Lines changed: 11 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -472,27 +472,22 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
472472
break;
473473
// Fall through and handle them the same as zext/trunc.
474474
[[fallthrough]];
475-
case TargetOpcode::G_ASSERT_ZEXT:
476475
case TargetOpcode::G_ZEXT:
477476
case TargetOpcode::G_TRUNC: {
478477
Register SrcReg = MI.getOperand(1).getReg();
479-
LLT SrcTy = MRI.getType(SrcReg);
480-
unsigned SrcBitWidth;
481-
482-
// G_ASSERT_ZEXT stores the original bitwidth in the immediate operand.
483-
if (Opcode == TargetOpcode::G_ASSERT_ZEXT)
484-
SrcBitWidth = MI.getOperand(2).getImm();
485-
else {
486-
SrcBitWidth = SrcTy.isPointer()
487-
? DL.getIndexSizeInBits(SrcTy.getAddressSpace())
488-
: SrcTy.getSizeInBits();
489-
}
490-
assert(SrcBitWidth && "SrcBitWidth can't be zero");
491-
Known = Known.zextOrTrunc(SrcBitWidth);
492478
computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
493479
Known = Known.zextOrTrunc(BitWidth);
494-
if (BitWidth > SrcBitWidth)
495-
Known.Zero.setBitsFrom(SrcBitWidth);
480+
break;
481+
}
482+
case TargetOpcode::G_ASSERT_ZEXT: {
483+
Register SrcReg = MI.getOperand(1).getReg();
484+
computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
485+
486+
unsigned SrcBitWidth = MI.getOperand(2).getImm();
487+
assert(SrcBitWidth && "SrcBitWidth can't be zero");
488+
APInt InMask = APInt::getLowBitsSet(BitWidth, SrcBitWidth);
489+
Known.Zero |= (~InMask);
490+
Known.One &= (~Known.Zero);
496491
break;
497492
}
498493
case TargetOpcode::G_ASSERT_ALIGN: {

‎llvm/test/CodeGen/AArch64/GlobalISel/knownbits-assertzext.mir

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple aarch64 -mattr=+sve -passes="print<gisel-value-tracking>" %s -o - 2>&1 | FileCheck %s
3+
4+
---
5+
name: ScalarConst
6+
body: |
7+
bb.0:
8+
; CHECK-LABEL: name: @ScalarConst
9+
; CHECK-NEXT: %0:_ KnownBits:10101001100001110110010101000011 SignBits:1
10+
; CHECK-NEXT: %1:_ KnownBits:00000000000000000110010101000011 SignBits:17
11+
%0:_(s32) = G_CONSTANT i32 2844222787
12+
%1:_(s32) = G_ASSERT_ZEXT %0(s32), 16
13+
...
14+
---
15+
name: ScalarVar
16+
body: |
17+
bb.0:
18+
; CHECK-LABEL: name: @ScalarVar
19+
; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
20+
; CHECK-NEXT: %1:_ KnownBits:0000000000000000???????????????? SignBits:16
21+
%0:_(s32) = COPY $w0
22+
%1:_(s32) = G_ASSERT_ZEXT %0(s32), 16
23+
...
24+
---
25+
name: VectorCst
26+
body: |
27+
bb.0:
28+
; CHECK-LABEL: name: @VectorCst
29+
; CHECK-NEXT: %0:_ KnownBits:10101001100001110110010101000011 SignBits:1
30+
; CHECK-NEXT: %1:_ KnownBits:10101001100001110110010101000011 SignBits:1
31+
; CHECK-NEXT: %2:_ KnownBits:00000000000000000110010101000011 SignBits:17
32+
%0:_(s32) = G_CONSTANT i32 2844222787
33+
%1:_(<4 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0
34+
%2:_(<4 x s32>) = G_ASSERT_ZEXT %1(<4 x s32>), 16
35+
...
36+
---
37+
name: VectorVar
38+
body: |
39+
bb.0:
40+
; CHECK-LABEL: name: @VectorVar
41+
; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
42+
; CHECK-NEXT: %1:_ KnownBits:0000000000000000???????????????? SignBits:16
43+
%0:_(<4 x s32>) = COPY $q0
44+
%1:_(<4 x s32>) = G_ASSERT_ZEXT %0(<4 x s32>), 16
45+
...
46+
---
47+
name: ScalableCst
48+
body: |
49+
bb.0:
50+
; CHECK-LABEL: name: @ScalableCst
51+
; CHECK-NEXT: %0:_ KnownBits:10101001100001110110010101000011 SignBits:1
52+
; CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1
53+
; CHECK-NEXT: %2:_ KnownBits:0000000000000000???????????????? SignBits:16
54+
%0:_(s32) = G_CONSTANT i32 2844222787
55+
%1:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %0
56+
%2:_(<vscale x 4 x s32>) = G_ASSERT_ZEXT %1(<vscale x 4 x s32>), 16
57+
...
58+
---
59+
name: ScalableVar
60+
body: |
61+
bb.0:
62+
; CHECK-LABEL: name: @ScalableVar
63+
; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
64+
; CHECK-NEXT: %1:_ KnownBits:0000000000000000???????????????? SignBits:16
65+
%0:_(<vscale x 4 x s32>) = COPY $z0
66+
%1:_(<vscale x 4 x s32>) = G_ASSERT_ZEXT %0(<vscale x 4 x s32>), 16
67+
...

‎llvm/test/CodeGen/AArch64/GlobalISel/knownbits-trunk.mir

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple aarch64 -mattr=+sve -passes="print<gisel-value-tracking>" %s -o - 2>&1 | FileCheck %s
3+
4+
---
5+
name: ScalarConst
6+
body: |
7+
bb.0:
8+
; CHECK-LABEL: name: @ScalarConst
9+
; CHECK-NEXT: %0:_ KnownBits:10101001100001110110010101000011 SignBits:1
10+
; CHECK-NEXT: %1:_ KnownBits:0110010101000011 SignBits:1
11+
%0:_(s32) = G_CONSTANT i32 2844222787
12+
%1:_(s16) = G_TRUNC %0(s32)
13+
...
14+
---
15+
name: ScalarVar
16+
body: |
17+
bb.0:
18+
; CHECK-LABEL: name: @ScalarVar
19+
; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
20+
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
21+
%0:_(s32) = COPY $w0
22+
%1:_(s16) = G_TRUNC %0(s32)
23+
...
24+
---
25+
name: VectorCst
26+
body: |
27+
bb.0:
28+
; CHECK-LABEL: name: @VectorCst
29+
; CHECK-NEXT: %0:_ KnownBits:10101001100001110110010101000011 SignBits:1
30+
; CHECK-NEXT: %1:_ KnownBits:10101001100001110110010101000011 SignBits:1
31+
; CHECK-NEXT: %2:_ KnownBits:0110010101000011 SignBits:1
32+
%0:_(s32) = G_CONSTANT i32 2844222787
33+
%1:_(<4 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0
34+
%2:_(<4 x s16>) = G_TRUNC %1(<4 x s32>)
35+
...
36+
---
37+
name: VectorVar
38+
body: |
39+
bb.0:
40+
; CHECK-LABEL: name: @VectorVar
41+
; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
42+
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
43+
%0:_(<4 x s32>) = COPY $q0
44+
%1:_(<4 x s16>) = G_TRUNC %0(<4 x s32>)
45+
...
46+
---
47+
name: ScalableCst
48+
body: |
49+
bb.0:
50+
; CHECK-LABEL: name: @ScalableCst
51+
; CHECK-NEXT: %0:_ KnownBits:10101001100001110110010101000011 SignBits:1
52+
; CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1
53+
; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:1
54+
%0:_(s32) = G_CONSTANT i32 2844222787
55+
%1:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %0
56+
%2:_(<vscale x 4 x s16>) = G_TRUNC %1(<vscale x 4 x s32>)
57+
...
58+
---
59+
name: ScalableVar
60+
body: |
61+
bb.0:
62+
; CHECK-LABEL: name: @ScalableVar
63+
; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
64+
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
65+
%0:_(<vscale x 4 x s32>) = COPY $z0
66+
%1:_(<vscale x 4 x s16>) = G_TRUNC %0(<vscale x 4 x s32>)
67+
...

‎llvm/test/CodeGen/AArch64/GlobalISel/knownbits-zext.mir

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple aarch64 -mattr=+sve -passes="print<gisel-value-tracking>" %s -o - 2>&1 | FileCheck %s
3+
4+
---
5+
name: ScalarConst
6+
body: |
7+
bb.0:
8+
; CHECK-LABEL: name: @ScalarConst
9+
; CHECK-NEXT: %0:_ KnownBits:0000000000001010 SignBits:12
10+
; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001010 SignBits:28
11+
%0:_(s16) = G_CONSTANT i16 10
12+
%1:_(s32) = G_ZEXT %0(s16)
13+
...
14+
---
15+
name: ScalarVar
16+
body: |
17+
bb.0:
18+
; CHECK-LABEL: name: @ScalarVar
19+
; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
20+
; CHECK-NEXT: %1:_ KnownBits:0000000000000000???????????????? SignBits:16
21+
%0:_(s16) = COPY $h0
22+
%1:_(s32) = G_ZEXT %0(s16)
23+
...
24+
---
25+
name: VectorCst
26+
body: |
27+
bb.0:
28+
; CHECK-LABEL: name: @VectorCst
29+
; CHECK-NEXT: %0:_ KnownBits:0000000000001010 SignBits:12
30+
; CHECK-NEXT: %1:_ KnownBits:0000000000001010 SignBits:12
31+
; CHECK-NEXT: %2:_ KnownBits:00000000000000000000000000001010 SignBits:28
32+
%0:_(s16) = G_CONSTANT i16 10
33+
%1:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
34+
%2:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
35+
...
36+
---
37+
name: VectorVar
38+
body: |
39+
bb.0:
40+
; CHECK-LABEL: name: @VectorVar
41+
; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
42+
; CHECK-NEXT: %1:_ KnownBits:0000000000000000???????????????? SignBits:16
43+
%0:_(<4 x s16>) = COPY $d0
44+
%1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
45+
...
46+
---
47+
name: ScalableCst
48+
body: |
49+
bb.0:
50+
; CHECK-LABEL: name: @ScalableCst
51+
; CHECK-NEXT: %0:_ KnownBits:0000000000001010 SignBits:12
52+
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
53+
; CHECK-NEXT: %2:_ KnownBits:0000000000000000???????????????? SignBits:16
54+
%0:_(s16) = G_CONSTANT i16 10
55+
%1:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR %0
56+
%2:_(<vscale x 4 x s32>) = G_ZEXT %1(<vscale x 4 x s16>)
57+
...
58+
---
59+
name: ScalableVar
60+
body: |
61+
bb.0:
62+
; CHECK-LABEL: name: @ScalableVar
63+
; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
64+
; CHECK-NEXT: %1:_ KnownBits:0000000000000000???????????????? SignBits:16
65+
%0:_(<vscale x 4 x s16>) = COPY $z0
66+
%1:_(<vscale x 4 x s32>) = G_ZEXT %0(<vscale x 4 x s16>)
67+
...

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