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UsmanNadeemUsmanNadeem
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test update after rebase
Change-Id: I317f5e81b27a588a98bbb9f93935575a18844caf
1 parent 7e0cafc commit 77a4342

5 files changed

+21
-21
lines changed

‎llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,8 @@ define <vscale x 4 x double> @mull_add(<vscale x 4 x double> %a, <vscale x 4 x d
1919
; CHECK-NEXT: fnmsb z0.d, p0/m, z2.d, z1.d
2020
; CHECK-NEXT: uzp2 z1.d, z4.d, z5.d
2121
; CHECK-NEXT: uzp1 z2.d, z4.d, z5.d
22-
; CHECK-NEXT: fadd z1.d, z3.d, z1.d
2322
; CHECK-NEXT: fadd z2.d, z2.d, z0.d
23+
; CHECK-NEXT: fadd z1.d, z3.d, z1.d
2424
; CHECK-NEXT: zip1 z0.d, z2.d, z1.d
2525
; CHECK-NEXT: zip2 z1.d, z2.d, z1.d
2626
; CHECK-NEXT: ret
@@ -223,17 +223,17 @@ define <vscale x 4 x double> @mul_add_rot_mull(<vscale x 4 x double> %a, <vscale
223223
; CHECK-NEXT: uzp1 z6.d, z6.d, z7.d
224224
; CHECK-NEXT: fmul z26.d, z0.d, z1.d
225225
; CHECK-NEXT: fmul z1.d, z25.d, z1.d
226-
; CHECK-NEXT: movprfx z7, z26
227-
; CHECK-NEXT: fmla z7.d, p0/m, z25.d, z2.d
228226
; CHECK-NEXT: fmul z3.d, z4.d, z24.d
229227
; CHECK-NEXT: fmul z24.d, z5.d, z24.d
228+
; CHECK-NEXT: movprfx z7, z26
229+
; CHECK-NEXT: fmla z7.d, p0/m, z25.d, z2.d
230230
; CHECK-NEXT: fnmsb z0.d, p0/m, z2.d, z1.d
231231
; CHECK-NEXT: movprfx z1, z3
232232
; CHECK-NEXT: fmla z1.d, p0/m, z6.d, z5.d
233233
; CHECK-NEXT: movprfx z2, z24
234234
; CHECK-NEXT: fnmls z2.d, p0/m, z4.d, z6.d
235-
; CHECK-NEXT: fadd z1.d, z7.d, z1.d
236235
; CHECK-NEXT: fadd z2.d, z0.d, z2.d
236+
; CHECK-NEXT: fadd z1.d, z7.d, z1.d
237237
; CHECK-NEXT: zip1 z0.d, z2.d, z1.d
238238
; CHECK-NEXT: zip2 z1.d, z2.d, z1.d
239239
; CHECK-NEXT: ret

‎llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,12 +15,12 @@ define <vscale x 4 x half> @complex_mul_v4f16(<vscale x 4 x half> %a, <vscale x
1515
; CHECK-NEXT: uzp2 z4.d, z0.d, z2.d
1616
; CHECK-NEXT: uzp1 z0.d, z0.d, z2.d
1717
; CHECK-NEXT: uzp2 z2.d, z1.d, z3.d
18+
; CHECK-NEXT: uzp1 z1.d, z1.d, z3.d
1819
; CHECK-NEXT: movprfx z5, z2
1920
; CHECK-NEXT: fmul z5.h, p0/m, z5.h, z0.h
20-
; CHECK-NEXT: uzp1 z1.d, z1.d, z3.d
21+
; CHECK-NEXT: fmul z2.h, p0/m, z2.h, z4.h
2122
; CHECK-NEXT: movprfx z3, z5
2223
; CHECK-NEXT: fmla z3.h, p0/m, z1.h, z4.h
23-
; CHECK-NEXT: fmul z2.h, p0/m, z2.h, z4.h
2424
; CHECK-NEXT: fnmsb z0.h, p0/m, z1.h, z2.h
2525
; CHECK-NEXT: zip2 z1.d, z0.d, z3.d
2626
; CHECK-NEXT: zip1 z0.d, z0.d, z3.d

‎llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -152,8 +152,8 @@ define <2 x double> @streaming_compatible_with_neon_vectors(<2 x double> %arg) "
152152
; CHECK-NEXT: smstart sm
153153
; CHECK-NEXT: .LBB4_4:
154154
; CHECK-NEXT: add x8, sp, #16
155-
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
156155
; CHECK-NEXT: ptrue p0.d, vl2
156+
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
157157
; CHECK-NEXT: ldr z1, [x8] // 16-byte Folded Reload
158158
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
159159
; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d

‎llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1391,17 +1391,17 @@ define void @abs_v128i16(ptr %a) vscale_range(2,0) #0 {
13911391
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
13921392
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0, x9, lsl #1]
13931393
; CHECK-NEXT: ld1h { z2.h }, p0/z, [x0, x10, lsl #1]
1394-
; CHECK-NEXT: ld1h { z3.h }, p0/z, [x0, x11, lsl #1]
1395-
; CHECK-NEXT: ld1h { z4.h }, p0/z, [x0, x12, lsl #1]
13961394
; CHECK-NEXT: mov x13, #48 // =0x30
13971395
; CHECK-NEXT: mov x14, #16 // =0x10
1396+
; CHECK-NEXT: ld1h { z3.h }, p0/z, [x0, x11, lsl #1]
1397+
; CHECK-NEXT: ld1h { z4.h }, p0/z, [x0, x12, lsl #1]
13981398
; CHECK-NEXT: ld1h { z5.h }, p0/z, [x0, x13, lsl #1]
1399+
; CHECK-NEXT: ld1h { z6.h }, p0/z, [x0, x14, lsl #1]
13991400
; CHECK-NEXT: abs z0.h, p0/m, z0.h
14001401
; CHECK-NEXT: abs z1.h, p0/m, z1.h
14011402
; CHECK-NEXT: abs z2.h, p0/m, z2.h
14021403
; CHECK-NEXT: abs z3.h, p0/m, z3.h
14031404
; CHECK-NEXT: abs z4.h, p0/m, z4.h
1404-
; CHECK-NEXT: ld1h { z6.h }, p0/z, [x0, x14, lsl #1]
14051405
; CHECK-NEXT: st1h { z0.h }, p0, [x0, x8, lsl #1]
14061406
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
14071407
; CHECK-NEXT: st1h { z1.h }, p0, [x0, x9, lsl #1]

‎llvm/test/CodeGen/AArch64/sve-split-fcvt.ll

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,9 @@
66
define <vscale x 8 x float> @fcvts_nxv8f16(<vscale x 8 x half> %a) {
77
; CHECK-LABEL: fcvts_nxv8f16:
88
; CHECK: // %bb.0:
9-
; CHECK-NEXT: ptrue p0.s
109
; CHECK-NEXT: uunpklo z1.s, z0.h
1110
; CHECK-NEXT: uunpkhi z2.s, z0.h
11+
; CHECK-NEXT: ptrue p0.s
1212
; CHECK-NEXT: movprfx z0, z1
1313
; CHECK-NEXT: fcvt z0.s, p0/m, z1.h
1414
; CHECK-NEXT: movprfx z1, z2
@@ -21,9 +21,9 @@ define <vscale x 8 x float> @fcvts_nxv8f16(<vscale x 8 x half> %a) {
2121
define <vscale x 4 x double> @fcvtd_nxv4f16(<vscale x 4 x half> %a) {
2222
; CHECK-LABEL: fcvtd_nxv4f16:
2323
; CHECK: // %bb.0:
24-
; CHECK-NEXT: ptrue p0.d
2524
; CHECK-NEXT: uunpklo z1.d, z0.s
2625
; CHECK-NEXT: uunpkhi z2.d, z0.s
26+
; CHECK-NEXT: ptrue p0.d
2727
; CHECK-NEXT: movprfx z0, z1
2828
; CHECK-NEXT: fcvt z0.d, p0/m, z1.h
2929
; CHECK-NEXT: movprfx z1, z2
@@ -37,8 +37,8 @@ define <vscale x 8 x double> @fcvtd_nxv8f16(<vscale x 8 x half> %a) {
3737
; CHECK-LABEL: fcvtd_nxv8f16:
3838
; CHECK: // %bb.0:
3939
; CHECK-NEXT: uunpklo z1.s, z0.h
40-
; CHECK-NEXT: ptrue p0.d
4140
; CHECK-NEXT: uunpkhi z0.s, z0.h
41+
; CHECK-NEXT: ptrue p0.d
4242
; CHECK-NEXT: uunpklo z2.d, z1.s
4343
; CHECK-NEXT: uunpkhi z1.d, z1.s
4444
; CHECK-NEXT: uunpklo z3.d, z0.s
@@ -58,9 +58,9 @@ define <vscale x 8 x double> @fcvtd_nxv8f16(<vscale x 8 x half> %a) {
5858
define <vscale x 4 x double> @fcvtd_nxv4f32(<vscale x 4 x float> %a) {
5959
; CHECK-LABEL: fcvtd_nxv4f32:
6060
; CHECK: // %bb.0:
61-
; CHECK-NEXT: ptrue p0.d
6261
; CHECK-NEXT: uunpklo z1.d, z0.s
6362
; CHECK-NEXT: uunpkhi z2.d, z0.s
63+
; CHECK-NEXT: ptrue p0.d
6464
; CHECK-NEXT: movprfx z0, z1
6565
; CHECK-NEXT: fcvt z0.d, p0/m, z1.s
6666
; CHECK-NEXT: movprfx z1, z2
@@ -73,11 +73,11 @@ define <vscale x 4 x double> @fcvtd_nxv4f32(<vscale x 4 x float> %a) {
7373
define <vscale x 8 x double> @fcvtd_nxv8f32(<vscale x 8 x float> %a) {
7474
; CHECK-LABEL: fcvtd_nxv8f32:
7575
; CHECK: // %bb.0:
76-
; CHECK-NEXT: ptrue p0.d
7776
; CHECK-NEXT: uunpklo z2.d, z0.s
7877
; CHECK-NEXT: uunpkhi z3.d, z0.s
7978
; CHECK-NEXT: uunpklo z4.d, z1.s
8079
; CHECK-NEXT: uunpkhi z5.d, z1.s
80+
; CHECK-NEXT: ptrue p0.d
8181
; CHECK-NEXT: movprfx z0, z2
8282
; CHECK-NEXT: fcvt z0.d, p0/m, z2.s
8383
; CHECK-NEXT: movprfx z1, z3
@@ -195,9 +195,9 @@ define <vscale x 8 x i16> @fcvtzs_h_nxv8f64(<vscale x 8 x double> %a) {
195195
define <vscale x 4 x i64> @fcvtzs_d_nxv4f32(<vscale x 4 x float> %a) {
196196
; CHECK-LABEL: fcvtzs_d_nxv4f32:
197197
; CHECK: // %bb.0:
198-
; CHECK-NEXT: ptrue p0.d
199198
; CHECK-NEXT: uunpklo z1.d, z0.s
200199
; CHECK-NEXT: uunpkhi z2.d, z0.s
200+
; CHECK-NEXT: ptrue p0.d
201201
; CHECK-NEXT: movprfx z0, z1
202202
; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.s
203203
; CHECK-NEXT: movprfx z1, z2
@@ -210,11 +210,11 @@ define <vscale x 4 x i64> @fcvtzs_d_nxv4f32(<vscale x 4 x float> %a) {
210210
define <vscale x 16 x i32> @fcvtzs_s_nxv16f16(<vscale x 16 x half> %a) {
211211
; CHECK-LABEL: fcvtzs_s_nxv16f16:
212212
; CHECK: // %bb.0:
213-
; CHECK-NEXT: ptrue p0.s
214213
; CHECK-NEXT: uunpklo z2.s, z0.h
215214
; CHECK-NEXT: uunpkhi z3.s, z0.h
216215
; CHECK-NEXT: uunpklo z4.s, z1.h
217216
; CHECK-NEXT: uunpkhi z5.s, z1.h
217+
; CHECK-NEXT: ptrue p0.s
218218
; CHECK-NEXT: movprfx z0, z2
219219
; CHECK-NEXT: fcvtzs z0.s, p0/m, z2.h
220220
; CHECK-NEXT: movprfx z1, z3
@@ -247,9 +247,9 @@ define <vscale x 4 x i32> @fcvtzu_s_nxv4f64(<vscale x 4 x double> %a) {
247247
define <vscale x 4 x i64> @fcvtzu_d_nxv4f32(<vscale x 4 x float> %a) {
248248
; CHECK-LABEL: fcvtzu_d_nxv4f32:
249249
; CHECK: // %bb.0:
250-
; CHECK-NEXT: ptrue p0.d
251250
; CHECK-NEXT: uunpklo z1.d, z0.s
252251
; CHECK-NEXT: uunpkhi z2.d, z0.s
252+
; CHECK-NEXT: ptrue p0.d
253253
; CHECK-NEXT: movprfx z0, z1
254254
; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.s
255255
; CHECK-NEXT: movprfx z1, z2
@@ -295,8 +295,8 @@ define <vscale x 16 x float> @scvtf_s_nxv16i8(<vscale x 16 x i8> %a) {
295295
; CHECK-LABEL: scvtf_s_nxv16i8:
296296
; CHECK: // %bb.0:
297297
; CHECK-NEXT: sunpklo z1.h, z0.b
298-
; CHECK-NEXT: ptrue p0.s
299298
; CHECK-NEXT: sunpkhi z0.h, z0.b
299+
; CHECK-NEXT: ptrue p0.s
300300
; CHECK-NEXT: sunpklo z2.s, z1.h
301301
; CHECK-NEXT: sunpkhi z1.s, z1.h
302302
; CHECK-NEXT: sunpklo z3.s, z0.h
@@ -316,9 +316,9 @@ define <vscale x 16 x float> @scvtf_s_nxv16i8(<vscale x 16 x i8> %a) {
316316
define <vscale x 4 x double> @scvtf_d_nxv4i32(<vscale x 4 x i32> %a) {
317317
; CHECK-LABEL: scvtf_d_nxv4i32:
318318
; CHECK: // %bb.0:
319-
; CHECK-NEXT: ptrue p0.d
320319
; CHECK-NEXT: sunpklo z1.d, z0.s
321320
; CHECK-NEXT: sunpkhi z2.d, z0.s
321+
; CHECK-NEXT: ptrue p0.d
322322
; CHECK-NEXT: movprfx z0, z1
323323
; CHECK-NEXT: scvtf z0.d, p0/m, z1.d
324324
; CHECK-NEXT: movprfx z1, z2
@@ -378,9 +378,9 @@ define <vscale x 8 x half> @ucvtf_h_nxv8i64(<vscale x 8 x i64> %a) {
378378
define <vscale x 4 x double> @ucvtf_d_nxv4i32(<vscale x 4 x i32> %a) {
379379
; CHECK-LABEL: ucvtf_d_nxv4i32:
380380
; CHECK: // %bb.0:
381-
; CHECK-NEXT: ptrue p0.d
382381
; CHECK-NEXT: uunpklo z1.d, z0.s
383382
; CHECK-NEXT: uunpkhi z2.d, z0.s
383+
; CHECK-NEXT: ptrue p0.d
384384
; CHECK-NEXT: movprfx z0, z1
385385
; CHECK-NEXT: ucvtf z0.d, p0/m, z1.d
386386
; CHECK-NEXT: movprfx z1, z2

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