Replace Zba, Zbb and Zbs with B.

tclin914 · tclin914 · commit 7830bb83c161 · 2025-05-21T16:23:51.000+08:00
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -659,10 +659,8 @@ def ANDES_A25 : RISCVProcessorModel<"andes-a25",
                                      FeatureStdExtF,
                                      FeatureStdExtD,
                                      FeatureStdExtC,
-                                     FeatureStdExtZba,
-                                     FeatureStdExtZbb,
-                                     FeatureStdExtZbc,
-                                     FeatureStdExtZbs]>;
+                                     FeatureStdExtB,
+                                     FeatureStdExtZbc]>;
 
 def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
                                      NoSchedModel,
@@ -675,10 +673,8 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
                                       FeatureStdExtF,
                                       FeatureStdExtD,
                                       FeatureStdExtC,
-                                      FeatureStdExtZba,
-                                      FeatureStdExtZbb,
-                                      FeatureStdExtZbc,
-                                      FeatureStdExtZbs]>;
+                                      FeatureStdExtB,
+                                      FeatureStdExtZbc]>;
 
 def ANDES_N45 : RISCVProcessorModel<"andes-n45",
                                     NoSchedModel,
