@@ -1995,8 +1995,8 @@ bool AArch64InstructionSelector::selectVectorAshrLshr(
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bool AArch64InstructionSelector::selectVaStartAAPCS (
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MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const {
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- if (STI.isCallingConvWin64 (
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- MF. getFunction (). getCallingConv (), MF.getFunction ().isVarArg ()))
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+ if (STI.isCallingConvWin64 (MF. getFunction (). getCallingConv (),
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+ MF.getFunction ().isVarArg ()))
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return false ;
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// The layout of the va_list struct is specified in the AArch64 Procedure Call
@@ -2044,8 +2044,7 @@ bool AArch64InstructionSelector::selectVaStartAAPCS(
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.addImm (OffsetBytes / PtrSize)
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.addMemOperand (MF.getMachineMemOperand (
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MMO->getPointerInfo ().getWithOffset (OffsetBytes),
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- MachineMemOperand::MOStore, PtrSize,
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- MMO->getBaseAlign ()));
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+ MachineMemOperand::MOStore, PtrSize, MMO->getBaseAlign ()));
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constrainSelectedInstRegOperands (*MIB, TII, TRI, RBI);
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OffsetBytes += PtrSize;
@@ -2080,8 +2079,7 @@ bool AArch64InstructionSelector::selectVaStartAAPCS(
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.addImm (OffsetBytes / IntSize)
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.addMemOperand (MF.getMachineMemOperand (
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MMO->getPointerInfo ().getWithOffset (OffsetBytes),
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- MachineMemOperand::MOStore, IntSize,
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- MMO->getBaseAlign ()));
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+ MachineMemOperand::MOStore, IntSize, MMO->getBaseAlign ()));
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constrainSelectedInstRegOperands (*MIB, TII, TRI, RBI);
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OffsetBytes += IntSize;
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};
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