[X86] Add test case for interleave shuffle for sub/add

Author: LuoYuanke

llvm/test/CodeGen/X86/avx512-shuffles/shuffle-blend.ll

@@ -0,0 +1,61 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw %s -o - | FileCheck %s
+
+define <16 x i32> @shuffle_v8i64(<16 x i32> %t0, <16 x i32> %t1) {
+; CHECK-LABEL: shuffle_v8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpaddd %zmm1, %zmm0, %zmm2
+; CHECK-NEXT:    vpsubd %zmm1, %zmm0, %zmm0
+; CHECK-NEXT:    movb $-86, %al
+; CHECK-NEXT:    kmovd %eax, %k1
+; CHECK-NEXT:    vmovdqa64 %zmm0, %zmm2 {%k1}
+; CHECK-NEXT:    vmovdqa64 %zmm2, %zmm0
+; CHECK-NEXT:    retq
+entry:
+  %t2 = add nsw <16 x i32> %t0, %t1
+  %t3 = sub nsw <16 x i32> %t0, %t1
+  %t4 = shufflevector <16 x i32> %t2, <16 x i32> %t3, <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 4, i32 5, i32 22, i32 23, i32 8, i32 9, i32 26, i32 27, i32 12, i32 13, i32 30, i32 31>
+  ret <16 x i32> %t4
+}
+
+define <8 x i32> @shuffle_v4i64(<8 x i32> %t0, <8 x i32> %t1) {
+; CHECK-LABEL: shuffle_v4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpaddd %ymm1, %ymm0, %ymm2
+; CHECK-NEXT:    vpsubd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    vpblendd {{.*#+}} ymm0 = ymm2[0,1],ymm0[2,3],ymm2[4,5],ymm0[6,7]
+; CHECK-NEXT:    retq
+entry:
+  %t2 = add nsw <8 x i32> %t0, %t1
+  %t3 = sub nsw <8 x i32> %t0, %t1
+  %t4 = shufflevector <8 x i32> %t2, <8 x i32> %t3, <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 4, i32 5, i32 14, i32 15>
+  ret <8 x i32> %t4
+}
+
+define <4 x i32> @shuffle_v2i64(<4 x i32> %t0, <4 x i32> %t1) {
+; CHECK-LABEL: shuffle_v2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpaddd %xmm1, %xmm0, %xmm2
+; CHECK-NEXT:    vpsubd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vpblendd {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3]
+; CHECK-NEXT:    retq
+entry:
+  %t2 = add nsw <4 x i32> %t0, %t1
+  %t3 = sub nsw <4 x i32> %t0, %t1
+  %t4 = shufflevector <4 x i32> %t2, <4 x i32> %t3, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+  ret <4 x i32> %t4
+}
+
+define <2 x i32> @shuffle_v2i32(<2 x i32> %t0, <2 x i32> %t1) {
+; CHECK-LABEL: shuffle_v2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpaddd %xmm1, %xmm0, %xmm2
+; CHECK-NEXT:    vpsubd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2,3]
+; CHECK-NEXT:    retq
+entry:
+  %t2 = add nsw <2 x i32> %t0, %t1
+  %t3 = sub nsw <2 x i32> %t0, %t1
+  %t4 = shufflevector <2 x i32> %t2, <2 x i32> %t3, <2 x i32> <i32 0, i32 3>
+  ret <2 x i32> %t4
+}