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[msan] Precommit tests.
Precommit tests for overflowing and saturating arithmetic intrinsics.
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‎llvm/test/Instrumentation/MemorySanitizer/overflow.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s
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target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define {i64, i1} @test_sadd_with_overflow(i64 %a, i64 %b) #0 {
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; CHECK-LABEL: define { i64, i1 } @test_sadd_with_overflow(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
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; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0
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; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
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; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0:![0-9]+]]
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; CHECK: 3:
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; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]]
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; CHECK-NEXT: unreachable
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; CHECK: 4:
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; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret { i64, i1 } [[RES]]
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;
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%res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
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ret { i64, i1 } %res
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}
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define {i64, i1} @test_uadd_with_overflow(i64 %a, i64 %b) #0 {
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; CHECK-LABEL: define { i64, i1 } @test_uadd_with_overflow(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
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; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0
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; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
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; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
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; CHECK: 3:
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; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
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; CHECK-NEXT: unreachable
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; CHECK: 4:
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; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret { i64, i1 } [[RES]]
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;
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%res = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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ret { i64, i1 } %res
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}
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define {i64, i1} @test_smul_with_overflow(i64 %a, i64 %b) #0 {
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; CHECK-LABEL: define { i64, i1 } @test_smul_with_overflow(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
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; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0
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; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
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; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
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; CHECK: 3:
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; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
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; CHECK-NEXT: unreachable
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; CHECK: 4:
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; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret { i64, i1 } [[RES]]
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;
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%res = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %a, i64 %b)
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ret { i64, i1 } %res
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}
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define {i64, i1} @test_umul_with_overflow(i64 %a, i64 %b) #0 {
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; CHECK-LABEL: define { i64, i1 } @test_umul_with_overflow(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
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; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0
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; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
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; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
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; CHECK: 3:
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; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
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; CHECK-NEXT: unreachable
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; CHECK: 4:
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; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret { i64, i1 } [[RES]]
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;
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%res = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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ret { i64, i1 } %res
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}
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define {i64, i1} @test_ssub_with_overflow(i64 %a, i64 %b) #0 {
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; CHECK-LABEL: define { i64, i1 } @test_ssub_with_overflow(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
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; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0
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; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
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; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
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; CHECK: 3:
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; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
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; CHECK-NEXT: unreachable
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; CHECK: 4:
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; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret { i64, i1 } [[RES]]
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;
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%res = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
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ret { i64, i1 } %res
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}
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define {i64, i1} @test_usub_with_overflow(i64 %a, i64 %b) #0 {
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; CHECK-LABEL: define { i64, i1 } @test_usub_with_overflow(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
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; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0
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; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
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; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
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; CHECK: 3:
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; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
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; CHECK-NEXT: unreachable
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; CHECK: 4:
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; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret { i64, i1 } [[RES]]
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;
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%res = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
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ret { i64, i1 } %res
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}
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define {<4 x i32>, <4 x i1>} @test_sadd_with_overflow_vec(<4 x i32> %a, <4 x i32> %b) #0 {
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; CHECK-LABEL: define { <4 x i32>, <4 x i1> } @test_sadd_with_overflow_vec(
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; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128
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; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0
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; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128
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; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0
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; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
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; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]]
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; CHECK: 5:
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; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
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; CHECK-NEXT: unreachable
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; CHECK: 6:
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; CHECK-NEXT: [[RES:%.*]] = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> [[A]], <4 x i32> [[B]])
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; CHECK-NEXT: store { <4 x i32>, <4 x i1> } zeroinitializer, ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret { <4 x i32>, <4 x i1> } [[RES]]
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;
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%res = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b)
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ret { <4 x i32>, <4 x i1> } %res
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}
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attributes #0 = { sanitize_memory }
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;.
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; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 1000}
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;.

‎llvm/test/Instrumentation/MemorySanitizer/saturating.ll

Lines changed: 113 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s
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target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define i64 @test_sadd_sat(i64 %a, i64 %b) #0 {
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; CHECK-LABEL: define i64 @test_sadd_sat(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sadd.sat.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret i64 [[RES]]
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;
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%res = call i64 @llvm.sadd.sat(i64 %a, i64 %b)
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ret i64 %res
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}
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define i64 @test_uadd_sat(i64 %a, i64 %b) #0 {
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; CHECK-LABEL: define i64 @test_uadd_sat(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret i64 [[RES]]
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;
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%res = call i64 @llvm.uadd.sat(i64 %a, i64 %b)
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ret i64 %res
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}
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define i64 @test_ssub_sat(i64 %a, i64 %b) #0 {
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; CHECK-LABEL: define i64 @test_ssub_sat(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
40+
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ssub.sat.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret i64 [[RES]]
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;
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%res = call i64 @llvm.ssub.sat(i64 %a, i64 %b)
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ret i64 %res
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}
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define i64 @test_usub_sat(i64 %a, i64 %b) #0 {
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; CHECK-LABEL: define i64 @test_usub_sat(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret i64 [[RES]]
62+
;
63+
%res = call i64 @llvm.usub.sat(i64 %a, i64 %b)
64+
ret i64 %res
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}
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define i64 @test_sshl_sat(i64 %a, i64 %b) #0 {
68+
; CHECK-LABEL: define i64 @test_sshl_sat(
69+
; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
70+
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
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; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]
74+
; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sshl.sat.i64(i64 [[A]], i64 [[B]])
75+
; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret i64 [[RES]]
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;
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%res = call i64 @llvm.sshl.sat(i64 %a, i64 %b)
79+
ret i64 %res
80+
}
81+
82+
define i64 @test_ushl_sat(i64 %a, i64 %b) #0 {
83+
; CHECK-LABEL: define i64 @test_ushl_sat(
84+
; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
85+
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
86+
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
87+
; CHECK-NEXT: call void @llvm.donothing()
88+
; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]
89+
; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ushl.sat.i64(i64 [[A]], i64 [[B]])
90+
; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8
91+
; CHECK-NEXT: ret i64 [[RES]]
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;
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%res = call i64 @llvm.ushl.sat(i64 %a, i64 %b)
94+
ret i64 %res
95+
}
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97+
define <4 x i32> @test_sadd_sat_vec(<4 x i32> %a, <4 x i32> %b) #0 {
98+
; CHECK-LABEL: define <4 x i32> @test_sadd_sat_vec(
99+
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] {
100+
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8
101+
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8
102+
; CHECK-NEXT: call void @llvm.donothing()
103+
; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[A]], <4 x i32> [[B]])
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; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret <4 x i32> [[RES]]
107+
;
108+
%res = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
109+
ret <4 x i32> %res
110+
}
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attributes #0 = { sanitize_memory }

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