Skip to content

Commit 79508c6

Browse files
wangpc-ppwangpc-pp
committed
[RISCV] Convert some predicates to TIIPredicate
These predicates can also be used in macro fusion and scheduling model.
1 parent cb7030d commit 79508c6

File tree

7 files changed

+102
-71
lines changed

7 files changed

+102
-71
lines changed

‎llvm/lib/Target/RISCV/RISCV.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,12 @@ include "RISCVCallingConv.td"
3636
include "RISCVInstrInfo.td"
3737
include "GISel/RISCVRegisterBanks.td"
3838

39+
//===----------------------------------------------------------------------===//
40+
// Instruction predicates
41+
//===----------------------------------------------------------------------===//
42+
43+
include "RISCVInstrPredicates.td"
44+
3945
//===----------------------------------------------------------------------===//
4046
// RISC-V macro fusions.
4147
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 2 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -19909,23 +19909,6 @@ static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
1990919909
return BB;
1991019910
}
1991119911

19912-
static bool isSelectPseudo(MachineInstr &MI) {
19913-
switch (MI.getOpcode()) {
19914-
default:
19915-
return false;
19916-
case RISCV::Select_GPR_Using_CC_GPR:
19917-
case RISCV::Select_GPR_Using_CC_Imm:
19918-
case RISCV::Select_FPR16_Using_CC_GPR:
19919-
case RISCV::Select_FPR16INX_Using_CC_GPR:
19920-
case RISCV::Select_FPR32_Using_CC_GPR:
19921-
case RISCV::Select_FPR32INX_Using_CC_GPR:
19922-
case RISCV::Select_FPR64_Using_CC_GPR:
19923-
case RISCV::Select_FPR64INX_Using_CC_GPR:
19924-
case RISCV::Select_FPR64IN32X_Using_CC_GPR:
19925-
return true;
19926-
}
19927-
}
19928-
1992919912
static MachineBasicBlock *emitQuietFCMP(MachineInstr &MI, MachineBasicBlock *BB,
1993019913
unsigned RelOpcode, unsigned EqOpcode,
1993119914
const RISCVSubtarget &Subtarget) {
@@ -20121,7 +20104,7 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
2012120104
SequenceMBBI != E; ++SequenceMBBI) {
2012220105
if (SequenceMBBI->isDebugInstr())
2012320106
continue;
20124-
if (isSelectPseudo(*SequenceMBBI)) {
20107+
if (RISCVInstrInfo::isSelectPseudo(*SequenceMBBI)) {
2012520108
if (SequenceMBBI->getOperand(1).getReg() != LHS ||
2012620109
!SequenceMBBI->getOperand(2).isReg() ||
2012720110
SequenceMBBI->getOperand(2).getReg() != RHS ||
@@ -20198,7 +20181,7 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
2019820181
auto InsertionPoint = TailMBB->begin();
2019920182
while (SelectMBBI != SelectEnd) {
2020020183
auto Next = std::next(SelectMBBI);
20201-
if (isSelectPseudo(*SelectMBBI)) {
20184+
if (RISCVInstrInfo::isSelectPseudo(*SelectMBBI)) {
2020220185
// %Result = phi [ %TrueValue, HeadMBB ], [ %FalseValue, IfFalseMBB ]
2020320186
BuildMI(*TailMBB, InsertionPoint, SelectMBBI->getDebugLoc(),
2020420187
TII.get(RISCV::PHI), SelectMBBI->getOperand(0).getReg())

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 11 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -69,21 +69,6 @@ static unsigned getSEWOpNum(const MachineInstr &MI) {
6969
return RISCVII::getSEWOpNum(MI.getDesc());
7070
}
7171

72-
static bool isVectorConfigInstr(const MachineInstr &MI) {
73-
return MI.getOpcode() == RISCV::PseudoVSETVLI ||
74-
MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
75-
MI.getOpcode() == RISCV::PseudoVSETIVLI;
76-
}
77-
78-
/// Return true if this is 'vsetvli x0, x0, vtype' which preserves
79-
/// VL and only sets VTYPE.
80-
static bool isVLPreservingConfig(const MachineInstr &MI) {
81-
if (MI.getOpcode() != RISCV::PseudoVSETVLIX0)
82-
return false;
83-
assert(RISCV::X0 == MI.getOperand(1).getReg());
84-
return RISCV::X0 == MI.getOperand(0).getReg();
85-
}
86-
8772
static bool isFloatScalarMoveOrScalarSplatInstr(const MachineInstr &MI) {
8873
switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
8974
default:
@@ -979,7 +964,7 @@ void RISCVInsertVSETVLI::forwardVSETVLIAVL(VSETVLIInfo &Info) const {
979964
if (!Info.hasAVLReg())
980965
return;
981966
const MachineInstr *DefMI = Info.getAVLDefMI(LIS);
982-
if (!DefMI || !isVectorConfigInstr(*DefMI))
967+
if (!DefMI || !RISCVInstrInfo::isVectorConfigInstr(*DefMI))
983968
return;
984969
VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(*DefMI);
985970
if (!DefInstrInfo.hasSameVLMAX(Info))
@@ -1126,7 +1111,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
11261111
// same, we can use the X0, X0 form.
11271112
if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLReg()) {
11281113
if (const MachineInstr *DefMI = Info.getAVLDefMI(LIS);
1129-
DefMI && isVectorConfigInstr(*DefMI)) {
1114+
DefMI && RISCVInstrInfo::isVectorConfigInstr(*DefMI)) {
11301115
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
11311116
if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
11321117
auto MI = BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
@@ -1304,7 +1289,7 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
13041289
// reflect the changes MI might make.
13051290
void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
13061291
const MachineInstr &MI) const {
1307-
if (isVectorConfigInstr(MI)) {
1292+
if (RISCVInstrInfo::isVectorConfigInstr(MI)) {
13081293
Info = getInfoForVSETVLI(MI);
13091294
return;
13101295
}
@@ -1339,7 +1324,8 @@ bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB,
13391324
for (const MachineInstr &MI : MBB) {
13401325
transferBefore(Info, MI);
13411326

1342-
if (isVectorConfigInstr(MI) || RISCVII::hasSEWOp(MI.getDesc().TSFlags) ||
1327+
if (RISCVInstrInfo::isVectorConfigInstr(MI) ||
1328+
RISCVII::hasSEWOp(MI.getDesc().TSFlags) ||
13431329
isVectorCopy(ST->getRegisterInfo(), MI))
13441330
HadVectorOp = true;
13451331

@@ -1429,7 +1415,7 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
14291415
if (!Value)
14301416
return true;
14311417
MachineInstr *DefMI = LIS->getInstructionFromIndex(Value->def);
1432-
if (!DefMI || !isVectorConfigInstr(*DefMI))
1418+
if (!DefMI || !RISCVInstrInfo::isVectorConfigInstr(*DefMI))
14331419
return true;
14341420

14351421
// We found a VSET(I)VLI make sure it matches the output of the
@@ -1460,7 +1446,7 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
14601446
transferBefore(CurInfo, MI);
14611447

14621448
// If this is an explicit VSETVLI or VSETIVLI, update our state.
1463-
if (isVectorConfigInstr(MI)) {
1449+
if (RISCVInstrInfo::isVectorConfigInstr(MI)) {
14641450
// Conservatively, mark the VL and VTYPE as live.
14651451
assert(MI.getOperand(3).getReg() == RISCV::VL &&
14661452
MI.getOperand(4).getReg() == RISCV::VTYPE &&
@@ -1660,12 +1646,12 @@ bool RISCVInsertVSETVLI::canMutatePriorConfig(
16601646
// If the VL values aren't equal, return false if either a) the former is
16611647
// demanded, or b) we can't rewrite the former to be the later for
16621648
// implementation reasons.
1663-
if (!isVLPreservingConfig(MI)) {
1649+
if (!RISCVInstrInfo::isVLPreservingConfig(MI)) {
16641650
if (Used.VLAny)
16651651
return false;
16661652

16671653
if (Used.VLZeroness) {
1668-
if (isVLPreservingConfig(PrevMI))
1654+
if (RISCVInstrInfo::isVLPreservingConfig(PrevMI))
16691655
return false;
16701656
if (!getInfoForVSETVLI(PrevMI).hasEquallyZeroAVL(getInfoForVSETVLI(MI),
16711657
LIS))
@@ -1716,7 +1702,7 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
17161702

17171703
for (MachineInstr &MI : make_early_inc_range(reverse(MBB))) {
17181704

1719-
if (!isVectorConfigInstr(MI)) {
1705+
if (!RISCVInstrInfo::isVectorConfigInstr(MI)) {
17201706
Used.doUnion(getDemanded(MI, ST));
17211707
if (MI.isCall() || MI.isInlineAsm() ||
17221708
MI.modifiesRegister(RISCV::VL, /*TRI=*/nullptr) ||
@@ -1740,7 +1726,7 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
17401726
}
17411727

17421728
if (canMutatePriorConfig(MI, *NextMI, Used)) {
1743-
if (!isVLPreservingConfig(*NextMI)) {
1729+
if (!RISCVInstrInfo::isVLPreservingConfig(*NextMI)) {
17441730
Register DefReg = NextMI->getOperand(0).getReg();
17451731

17461732
MI.getOperand(0).setReg(DefReg);

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 6 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,9 @@ RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)
7777
: RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
7878
STI(STI) {}
7979

80+
#define GET_INSTRINFO_HELPERS
81+
#include "RISCVGenInstrInfo.inc"
82+
8083
MCInst RISCVInstrInfo::getNop() const {
8184
if (STI.hasStdExtCOrZca())
8285
return MCInstBuilder(RISCV::C_NOP);
@@ -777,15 +780,15 @@ MachineInstr *RISCVInstrInfo::foldMemoryOperandImpl(
777780
unsigned LoadOpc;
778781
switch (MI.getOpcode()) {
779782
default:
780-
if (RISCV::isSEXT_W(MI)) {
783+
if (RISCVInstrInfo::isSEXT_W(MI)) {
781784
LoadOpc = RISCV::LW;
782785
break;
783786
}
784-
if (RISCV::isZEXT_W(MI)) {
787+
if (RISCVInstrInfo::isZEXT_W(MI)) {
785788
LoadOpc = RISCV::LWU;
786789
break;
787790
}
788-
if (RISCV::isZEXT_B(MI)) {
791+
if (RISCVInstrInfo::isZEXT_B(MI)) {
789792
LoadOpc = RISCV::LBU;
790793
break;
791794
}
@@ -3991,24 +3994,6 @@ unsigned RISCVInstrInfo::getTailDuplicateSize(CodeGenOptLevel OptLevel) const {
39913994
: 2;
39923995
}
39933996

3994-
// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
3995-
bool RISCV::isSEXT_W(const MachineInstr &MI) {
3996-
return MI.getOpcode() == RISCV::ADDIW && MI.getOperand(1).isReg() &&
3997-
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0;
3998-
}
3999-
4000-
// Returns true if this is the zext.w pattern, adduw rd, rs1, x0.
4001-
bool RISCV::isZEXT_W(const MachineInstr &MI) {
4002-
return MI.getOpcode() == RISCV::ADD_UW && MI.getOperand(1).isReg() &&
4003-
MI.getOperand(2).isReg() && MI.getOperand(2).getReg() == RISCV::X0;
4004-
}
4005-
4006-
// Returns true if this is the zext.b pattern, andi rd, rs1, 255.
4007-
bool RISCV::isZEXT_B(const MachineInstr &MI) {
4008-
return MI.getOpcode() == RISCV::ANDI && MI.getOperand(1).isReg() &&
4009-
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 255;
4010-
}
4011-
40123997
static bool isRVVWholeLoadStore(unsigned Opcode) {
40133998
switch (Opcode) {
40143999
default:

‎llvm/lib/Target/RISCV/RISCVInstrInfo.h

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -301,6 +301,9 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
301301

302302
bool isHighLatencyDef(int Opc) const override;
303303

304+
#define GET_INSTRINFO_HELPER_DECLS
305+
#include "RISCVGenInstrInfo.inc"
306+
304307
protected:
305308
const RISCVSubtarget &STI;
306309

@@ -317,11 +320,6 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
317320

318321
namespace RISCV {
319322

320-
// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
321-
bool isSEXT_W(const MachineInstr &MI);
322-
bool isZEXT_W(const MachineInstr &MI);
323-
bool isZEXT_B(const MachineInstr &MI);
324-
325323
// Returns true if the given MI is an RVV instruction opcode for which we may
326324
// expect to see a FrameIndex operand.
327325
bool isRVVSpill(const MachineInstr &MI);

‎llvm/lib/Target/RISCV/RISCVInstrPredicates.td

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,73 @@
1+
//===-- RISCVInstrPredicates.td - Instruction Predicates ---*- tablegen -*-===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
//
9+
// This file describes the RISC-V instruction predicates.
10+
//
11+
//===----------------------------------------------------------------------===//
12+
13+
// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
14+
def isSEXT_W : TIIPredicate<"isSEXT_W",
15+
MCReturnStatement<CheckAll<[
16+
CheckOpcode<[ADDIW]>,
17+
CheckIsRegOperand<1>,
18+
CheckIsImmOperand<2>,
19+
CheckImmOperand<2, 0>
20+
]>>>;
21+
22+
// Returns true if this is the zext.w pattern, adduw rd, rs1, x0.
23+
def isZEXT_W : TIIPredicate<"isZEXT_W",
24+
MCReturnStatement<CheckAll<[
25+
CheckOpcode<[ADD_UW]>,
26+
CheckIsRegOperand<1>,
27+
CheckIsRegOperand<2>,
28+
CheckRegOperand<2, X0>
29+
]>>>;
30+
31+
// Returns true if this is the zext.b pattern, andi rd, rs1, 255.
32+
def isZEXT_B : TIIPredicate<"isZEXT_B",
33+
MCReturnStatement<CheckAll<[
34+
CheckOpcode<[ANDI]>,
35+
CheckIsRegOperand<1>,
36+
CheckIsImmOperand<2>,
37+
CheckImmOperand<2, 255>
38+
]>>>;
39+
40+
// Returns true if this is the zext.b pattern, andi rd, rs1, 255.
41+
def isSelectPseudo : TIIPredicate<"isSelectPseudo",
42+
MCOpcodeSwitchStatement<
43+
[MCOpcodeSwitchCase<
44+
[Select_GPR_Using_CC_GPR,
45+
Select_GPR_Using_CC_Imm,
46+
Select_FPR16_Using_CC_GPR,
47+
Select_FPR16INX_Using_CC_GPR,
48+
Select_FPR32_Using_CC_GPR,
49+
Select_FPR32INX_Using_CC_GPR,
50+
Select_FPR64_Using_CC_GPR,
51+
Select_FPR64INX_Using_CC_GPR,
52+
Select_FPR64IN32X_Using_CC_GPR
53+
],
54+
MCReturnStatement<TruePred>>],
55+
MCReturnStatement<FalsePred>>>;
56+
57+
// Returns true if this is a vector configuration instruction.
58+
def isVectorConfigInstr : TIIPredicate<"isVectorConfigInstr",
59+
MCReturnStatement<
60+
CheckOpcode<[
61+
PseudoVSETVLI,
62+
PseudoVSETVLIX0,
63+
PseudoVSETIVLI
64+
]>>>;
65+
66+
/// Return true if this is 'vsetvli x0, x0, vtype' which preserves
67+
/// VL and only sets VTYPE.
68+
def isVLPreservingConfig : TIIPredicate<"isVLPreservingConfig",
69+
MCReturnStatement<
70+
CheckAll<[
71+
CheckOpcode<[PseudoVSETVLIX0]>,
72+
CheckRegOperand<0, X0>
73+
]>>>;

‎llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -648,7 +648,7 @@ bool RISCVOptWInstrs::removeSExtWInstrs(MachineFunction &MF,
648648
for (MachineBasicBlock &MBB : MF) {
649649
for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
650650
// We're looking for the sext.w pattern ADDIW rd, rs1, 0.
651-
if (!RISCV::isSEXT_W(MI))
651+
if (!RISCVInstrInfo::isSEXT_W(MI))
652652
continue;
653653

654654
Register SrcReg = MI.getOperand(1).getReg();

0 commit comments

Comments
 (0)