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[FMV] Remove feature dgh. (#115363)
It belongs to the HINT space so it can be executed as NOP if the hardware doesn't support it. Reviewed in ACLE -> ARM-software/acle#357
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9 files changed

+13
-36
lines changed

9 files changed

+13
-36
lines changed

‎clang/test/CodeGen/aarch64-cpu-supports-target.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ int check_all_feature() {
77
return 2;
88
else if (__builtin_cpu_supports("aes+pmull+fp16+dit+dpb+dpb2+jscvt"))
99
return 3;
10-
else if (__builtin_cpu_supports("fcma+rcpc+rcpc2+rcpc3+frintts+dgh"))
10+
else if (__builtin_cpu_supports("fcma+rcpc+rcpc2+rcpc3+frintts"))
1111
return 4;
1212
else if (__builtin_cpu_supports("i8mm+bf16+sve"))
1313
return 5;

‎clang/test/CodeGen/aarch64-fmv-dependencies.c

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,9 +15,6 @@ __attribute__((target_version("bti"))) int fmv(void) { return 0; }
1515
// CHECK: define dso_local i32 @fmv._Mcrc() #[[crc:[0-9]+]] {
1616
__attribute__((target_version("crc"))) int fmv(void) { return 0; }
1717

18-
// CHECK: define dso_local i32 @fmv._Mdgh() #[[ATTR0:[0-9]+]] {
19-
__attribute__((target_version("dgh"))) int fmv(void) { return 0; }
20-
2118
// CHECK: define dso_local i32 @fmv._Mdit() #[[dit:[0-9]+]] {
2219
__attribute__((target_version("dit"))) int fmv(void) { return 0; }
2320

@@ -157,7 +154,6 @@ int caller() {
157154
// CHECK: attributes #[[bf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+v8a"
158155
// CHECK: attributes #[[bti]] = { {{.*}} "target-features"="+bti,+fp-armv8,+neon,+outline-atomics,+v8a"
159156
// CHECK: attributes #[[crc]] = { {{.*}} "target-features"="+crc,+fp-armv8,+neon,+outline-atomics,+v8a"
160-
// CHECK: attributes #[[ATTR0]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a"
161157
// CHECK: attributes #[[dit]] = { {{.*}} "target-features"="+dit,+fp-armv8,+neon,+outline-atomics,+v8a"
162158
// CHECK: attributes #[[dotprod]] = { {{.*}} "target-features"="+dotprod,+fp-armv8,+neon,+outline-atomics,+v8a"
163159
// CHECK: attributes #[[dpb]] = { {{.*}} "target-features"="+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a"
@@ -167,6 +163,7 @@ int caller() {
167163
// CHECK: attributes #[[fcma]] = { {{.*}} "target-features"="+complxnum,+fp-armv8,+neon,+outline-atomics,+v8a"
168164
// CHECK: attributes #[[flagm]] = { {{.*}} "target-features"="+flagm,+fp-armv8,+neon,+outline-atomics,+v8a"
169165
// CHECK: attributes #[[flagm2]] = { {{.*}} "target-features"="+altnzcv,+flagm,+fp-armv8,+neon,+outline-atomics,+v8a"
166+
// CHECK: attributes #[[ATTR0]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a"
170167
// CHECK: attributes #[[fp16]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+v8a"
171168
// CHECK: attributes #[[fp16fml]] = { {{.*}} "target-features"="+fp-armv8,+fp16fml,+fullfp16,+neon,+outline-atomics,+v8a"
172169
// CHECK: attributes #[[frintts]] = { {{.*}} "target-features"="+fp-armv8,+fptoint,+neon,+outline-atomics,+v8a"

‎clang/test/CodeGen/attr-target-version.c

Lines changed: 6 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,6 @@ int __attribute__((target_version("dpb"))) fmv_one(void) { return 2; }
1717
int __attribute__((target_version("default"))) fmv_one(void) { return 0; }
1818
int __attribute__((target_version("fp"))) fmv_two(void) { return 1; }
1919
int __attribute__((target_version("simd"))) fmv_two(void) { return 2; }
20-
int __attribute__((target_version("dgh"))) fmv_two(void) { return 3; }
2120
int __attribute__((target_version("fp16+simd"))) fmv_two(void) { return 4; }
2221
int __attribute__((target_version("default"))) fmv_two(void) { return 0; }
2322
int foo() {
@@ -255,13 +254,6 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
255254
//
256255
//
257256
// CHECK: Function Attrs: noinline nounwind optnone
258-
// CHECK-LABEL: define {{[^@]+}}@fmv_two._Mdgh
259-
// CHECK-SAME: () #[[ATTR9]] {
260-
// CHECK-NEXT: entry:
261-
// CHECK-NEXT: ret i32 3
262-
//
263-
//
264-
// CHECK: Function Attrs: noinline nounwind optnone
265257
// CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp16Msimd
266258
// CHECK-SAME: () #[[ATTR13:[0-9]+]] {
267259
// CHECK-NEXT: entry:
@@ -576,29 +568,21 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
576568
// CHECK-NEXT: ret ptr @fmv_two._Mfp16Msimd
577569
// CHECK: resolver_else:
578570
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
579-
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 33554432
580-
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 33554432
571+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 512
572+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 512
581573
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
582574
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
583575
// CHECK: resolver_return1:
584-
// CHECK-NEXT: ret ptr @fmv_two._Mdgh
576+
// CHECK-NEXT: ret ptr @fmv_two._Msimd
585577
// CHECK: resolver_else2:
586578
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
587-
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 512
588-
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 512
579+
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 256
580+
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 256
589581
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
590582
// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
591583
// CHECK: resolver_return3:
592-
// CHECK-NEXT: ret ptr @fmv_two._Msimd
593-
// CHECK: resolver_else4:
594-
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
595-
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 256
596-
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 256
597-
// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
598-
// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
599-
// CHECK: resolver_return5:
600584
// CHECK-NEXT: ret ptr @fmv_two._Mfp
601-
// CHECK: resolver_else6:
585+
// CHECK: resolver_else4:
602586
// CHECK-NEXT: ret ptr @fmv_two.default
603587
//
604588
//

‎clang/test/Sema/aarch64-cpu-supports.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ int test_aarch64_features(void) {
1515
if (__builtin_cpu_supports("sve2,sve"))
1616
return 4;
1717
// expected-warning@+1 {{invalid cpu feature string}}
18-
if (__builtin_cpu_supports("dgh+sve2-pmull"))
18+
if (__builtin_cpu_supports("aes+sve2-pmull"))
1919
return 5;
2020
// expected-warning@+1 {{invalid cpu feature string}}
2121
if (__builtin_cpu_supports("default"))

‎clang/test/Sema/attr-target-clones-aarch64.c

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,10 +19,9 @@ int __attribute__((target_clones("sve+dotprod"))) redecl3(void);
1919
int redecl3(void);
2020

2121
int __attribute__((target_clones("rng", "fp16fml+fp", "default"))) redecl4(void);
22-
// expected-error@+3 {{'target_clones' attribute does not match previous declaration}}
22+
// expected-error@+2 {{'target_clones' attribute does not match previous declaration}}
2323
// expected-note@-2 {{previous declaration is here}}
24-
// expected-warning@+1 {{version list contains entries that don't impact code generation}}
25-
int __attribute__((target_clones("dgh", "bf16+dpb", "default"))) redecl4(void) { return 1; }
24+
int __attribute__((target_clones("dit", "bf16+dpb", "default"))) redecl4(void) { return 1; }
2625

2726
int __attribute__((target_version("flagm2"))) redef2(void) { return 1; }
2827
// expected-error@+2 {{multiversioned function redeclarations require identical target attributes}}

‎compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ enum CPUFeatures {
4747
FEAT_RCPC,
4848
FEAT_RCPC2,
4949
FEAT_FRINTTS,
50-
FEAT_DGH,
50+
RESERVED_FEAT_DGH, // previously used and now ABI legacy
5151
FEAT_I8MM,
5252
FEAT_BF16,
5353
RESERVED_FEAT_EBF16, // previously used and now ABI legacy

‎compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -61,8 +61,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
6161
setCPUFeature(FEAT_RNG);
6262
if (hwcap2 & HWCAP2_I8MM)
6363
setCPUFeature(FEAT_I8MM);
64-
if (hwcap2 & HWCAP2_DGH)
65-
setCPUFeature(FEAT_DGH);
6664
if (hwcap2 & HWCAP2_FRINT)
6765
setCPUFeature(FEAT_FRINTTS);
6866
if (hwcap2 & HWCAP2_SVEF32MM)

‎llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ enum CPUFeatures {
4747
FEAT_RCPC,
4848
FEAT_RCPC2,
4949
FEAT_FRINTTS,
50-
FEAT_DGH,
50+
RESERVED_FEAT_DGH, // previously used and now ABI legacy
5151
FEAT_I8MM,
5252
FEAT_BF16,
5353
RESERVED_FEAT_EBF16, // previously used and now ABI legacy

‎llvm/lib/Target/AArch64/AArch64FMV.td

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,6 @@ def : FMVExtension<"aes", "FEAT_PMULL", "+aes,+fp-armv8,+neon", 150>;
4141
def : FMVExtension<"bf16", "FEAT_BF16", "+bf16", 280>;
4242
def : FMVExtension<"bti", "FEAT_BTI", "+bti", 510>;
4343
def : FMVExtension<"crc", "FEAT_CRC", "+crc", 110>;
44-
def : FMVExtension<"dgh", "FEAT_DGH", "", 260>;
4544
def : FMVExtension<"dit", "FEAT_DIT", "+dit", 180>;
4645
def : FMVExtension<"dotprod", "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>;
4746
def : FMVExtension<"dpb", "FEAT_DPB", "+ccpp", 190>;

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