@@ -36,13 +36,9 @@ class GenericMachineInstr : public MachineInstr {
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}
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};
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- // / Represents any type of generic load or store.
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- // / G_LOAD, G_STORE, G_ZEXTLOAD, G_SEXTLOAD.
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- class GLoadStore : public GenericMachineInstr {
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+ // / Provides common memory operand functionality.
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+ class GMemOperation : public GenericMachineInstr {
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public:
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- // / Get the source register of the pointer value.
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- Register getPointerReg () const { return getOperand (1 ).getReg (); }
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-
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// / Get the MachineMemOperand on this instruction.
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MachineMemOperand &getMMO () const { return **memoperands_begin (); }
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@@ -62,6 +58,18 @@ class GLoadStore : public GenericMachineInstr {
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} // / Returns the size in bits of the memory access.
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uint64_t getMemSizeInBits () const { return getMMO ().getSizeInBits (); }
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+ static bool classof (const MachineInstr *MI) {
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+ return GenericMachineInstr::classof (MI) && MI->hasOneMemOperand ();
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+ }
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+ };
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+
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+ // / Represents any type of generic load or store.
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+ // / G_LOAD, G_STORE, G_ZEXTLOAD, G_SEXTLOAD.
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+ class GLoadStore : public GMemOperation {
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+ public:
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+ // / Get the source register of the pointer value.
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+ Register getPointerReg () const { return getOperand (1 ).getReg (); }
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+
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static bool classof (const MachineInstr *MI) {
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switch (MI->getOpcode ()) {
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case TargetOpcode::G_LOAD:
@@ -75,6 +83,73 @@ class GLoadStore : public GenericMachineInstr {
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}
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};
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+ // / Represents indexed loads. These are different enough from regular loads
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+ // / that they get their own class. Including them in GAnyLoad would probably
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+ // / make a footgun for someone.
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+ class GIndexedLoad : public GMemOperation {
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+ public:
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+ // / Get the definition register of the loaded value.
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+ Register getDstReg () const { return getOperand (0 ).getReg (); }
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+ // / Get the def register of the writeback value.
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+ Register getWritebackReg () const { return getOperand (1 ).getReg (); }
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+ // / Get the base register of the pointer value.
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+ Register getBaseReg () const { return getOperand (2 ).getReg (); }
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+ // / Get the offset register of the pointer value.
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+ Register getOffsetReg () const { return getOperand (3 ).getReg (); }
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+
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+ bool isPre () const { return getOperand (5 ).getImm () == 1 ; }
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+ bool isPost () const { return !isPre (); }
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+
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+ static bool classof (const MachineInstr *MI) {
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+ return MI->getOpcode () == TargetOpcode::G_INDEXED_LOAD;
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+ }
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+ };
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+
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+ // / Represents a G_INDEX_ZEXTLOAD/G_INDEXED_SEXTLOAD.
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+ class GIndexedExtLoad : public GIndexedLoad {
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+ public:
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+ static bool classof (const MachineInstr *MI) {
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+ return MI->getOpcode () == TargetOpcode::G_INDEXED_SEXTLOAD ||
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+ MI->getOpcode () == TargetOpcode::G_INDEXED_ZEXTLOAD;
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+ }
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+ };
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+
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+ // / Represents a G_ZEXTLOAD.
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+ class GIndexedZExtLoad : GIndexedExtLoad {
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+ public:
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+ static bool classof (const MachineInstr *MI) {
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+ return MI->getOpcode () == TargetOpcode::G_INDEXED_ZEXTLOAD;
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+ }
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+ };
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+
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+ // / Represents a G_SEXTLOAD.
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+ class GIndexedSExtLoad : GIndexedExtLoad {
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+ public:
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+ static bool classof (const MachineInstr *MI) {
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+ return MI->getOpcode () == TargetOpcode::G_INDEXED_SEXTLOAD;
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+ }
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+ };
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+
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+ // / Represents indexed stores.
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+ class GIndexedStore : public GMemOperation {
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+ public:
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+ // / Get the def register of the writeback value.
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+ Register getWritebackReg () const { return getOperand (0 ).getReg (); }
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+ // / Get the stored value register.
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+ Register getValueReg () const { return getOperand (1 ).getReg (); }
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+ // / Get the base register of the pointer value.
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+ Register getBaseReg () const { return getOperand (2 ).getReg (); }
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+ // / Get the offset register of the pointer value.
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+ Register getOffsetReg () const { return getOperand (3 ).getReg (); }
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+
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+ bool isPre () const { return getOperand (4 ).getImm () == 1 ; }
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+ bool isPost () const { return !isPre (); }
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+
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+ static bool classof (const MachineInstr *MI) {
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+ return MI->getOpcode () == TargetOpcode::G_INDEXED_STORE;
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+ }
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+ };
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+
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// / Represents any generic load, including sign/zero extending variants.
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class GAnyLoad : public GLoadStore {
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public:
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