update predicates

XinWang10 · XinWang10 · commit 79d2fc0aa2a2 · 2024-01-18T22:02:37.000-08:00
diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td
@@ -229,7 +229,7 @@ def PUSHA16  : I<0x60, RawFrm, (outs), (ins), "pushaw", []>,
                OpSize16, Requires<[Not64BitMode]>;
 }
 
-let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32] in {
+let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32], Predicates = [NoEGPR] in {
 // This instruction is a consequence of BSWAP32r observing operand size. The
 // encoding is valid, but the behavior is undefined.
 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
diff --git a/llvm/test/CodeGen/X86/movbe.ll b/llvm/test/CodeGen/X86/movbe.ll
@@ -182,8 +182,7 @@ define i64 @test7(i64 %x) nounwind {
 ;
 ; EGPR-LABEL: test7:
 ; EGPR:       # %bb.0:
-; EGPR-NEXT:    movq %rdi, %rax # encoding: [0x48,0x89,0xf8]
-; EGPR-NEXT:    bswapq %rax # encoding: [0x48,0x0f,0xc8]
+; EGPR-NEXT:    movbeq %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x08,0x61,0xf8]
 ; EGPR-NEXT:    retq # encoding: [0xc3]
   %bswap = call i64 @llvm.bswap.i64(i64 %x)
   ret i64 %bswap

Original file line number	Diff line number	Diff line change
`@@ -229,7 +229,7 @@ def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", []>,`
`229`	`229`	`OpSize16, Requires<[Not64BitMode]>;`
`230`	`230`	`}`
`231`	`231`
`232`		`-let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32] in {`
	`232`	`+let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32], Predicates = [NoEGPR] in {`
`233`	`233`	`// This instruction is a consequence of BSWAP32r observing operand size. The`
`234`	`234`	`// encoding is valid, but the behavior is undefined.`
`235`	`235`	`let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in`