[RISCV][GlobalISel] Select G_FRAME_INDEX

Author: nitinjohnraj

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

@@ -239,6 +239,18 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
   }
   case TargetOpcode::G_SEXT_INREG:
     return selectSExtInreg(MI, MIB);
+  case TargetOpcode::G_FRAME_INDEX: {
+    // FIXME: We want to replace this with tablegen code that matches for
+    // FrameAddrRegImm
+    Register DstReg = MI.getOperand(0).getReg();
+
+    if (!MRI.getType(DstReg).isPointer())
+      return false;
+
+    MI.setDesc(TII.get(RISCV::ADDI));
+    MI.addOperand(MachineOperand::CreateImm(0));
+    return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
+  }
   default:
     return false;
   }

llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

@@ -127,6 +127,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_STORE:
     break;
   case TargetOpcode::G_CONSTANT:
+  case TargetOpcode::G_FRAME_INDEX:
   case TargetOpcode::G_GLOBAL_VALUE:
   case TargetOpcode::G_BRCOND:
     OperandsMapping = getOperandsMapping({GPRValueMapping, nullptr});

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir

@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+  define ptr @frame_index() {
+  entry:
+    %x = alloca i32, align 4
+    ret ptr %x
+  }
+
+...
+---
+name:            frame_index
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: gprb, preferred-register: '' }
+stack:
+  - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: frame_index
+    ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+    $x10 = COPY %0(p0)
+    PseudoRET implicit $x10
+
+...

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir

@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+  define ptr @frame_index() {
+  entry:
+    %x = alloca i32, align 4
+    ret ptr %x
+  }
+
+...
+---
+name:            frame_index
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: gprb, preferred-register: '' }
+stack:
+  - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: frame_index
+    ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+    $x10 = COPY %0(p0)
+    PseudoRET implicit $x10
+
+...