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Reland "[InstCombine] Extend foldICmpBinOp to add-like or" (#76531)
The original PR had a typo which was causing a bug.
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2 files changed

+182
-53
lines changed

2 files changed

+182
-53
lines changed

‎llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp

Lines changed: 33 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -4629,27 +4629,35 @@ Instruction *InstCombinerImpl::foldICmpBinOp(ICmpInst &I,
46294629
}
46304630

46314631
bool NoOp0WrapProblem = false, NoOp1WrapProblem = false;
4632-
if (BO0 && isa<OverflowingBinaryOperator>(BO0))
4633-
NoOp0WrapProblem =
4634-
ICmpInst::isEquality(Pred) ||
4635-
(CmpInst::isUnsigned(Pred) && BO0->hasNoUnsignedWrap()) ||
4636-
(CmpInst::isSigned(Pred) && BO0->hasNoSignedWrap());
4637-
if (BO1 && isa<OverflowingBinaryOperator>(BO1))
4638-
NoOp1WrapProblem =
4639-
ICmpInst::isEquality(Pred) ||
4640-
(CmpInst::isUnsigned(Pred) && BO1->hasNoUnsignedWrap()) ||
4641-
(CmpInst::isSigned(Pred) && BO1->hasNoSignedWrap());
4642-
4632+
bool Op0HasNUW = false, Op1HasNUW = false;
4633+
bool Op0HasNSW = false, Op1HasNSW = false;
46434634
// Analyze the case when either Op0 or Op1 is an add instruction.
46444635
// Op0 = A + B (or A and B are null); Op1 = C + D (or C and D are null).
4636+
auto hasNoWrapProblem = [](const BinaryOperator &BO, CmpInst::Predicate Pred,
4637+
bool &HasNSW, bool &HasNUW) -> bool {
4638+
if (isa<OverflowingBinaryOperator>(BO)) {
4639+
HasNUW = BO.hasNoUnsignedWrap();
4640+
HasNSW = BO.hasNoSignedWrap();
4641+
return ICmpInst::isEquality(Pred) ||
4642+
(CmpInst::isUnsigned(Pred) && HasNUW) ||
4643+
(CmpInst::isSigned(Pred) && HasNSW);
4644+
} else if (BO.getOpcode() == Instruction::Or) {
4645+
HasNUW = true;
4646+
HasNSW = true;
4647+
return true;
4648+
} else {
4649+
return false;
4650+
}
4651+
};
46454652
Value *A = nullptr, *B = nullptr, *C = nullptr, *D = nullptr;
4646-
if (BO0 && BO0->getOpcode() == Instruction::Add) {
4647-
A = BO0->getOperand(0);
4648-
B = BO0->getOperand(1);
4653+
4654+
if (BO0) {
4655+
match(BO0, m_AddLike(m_Value(A), m_Value(B)));
4656+
NoOp0WrapProblem = hasNoWrapProblem(*BO0, Pred, Op0HasNSW, Op0HasNUW);
46494657
}
4650-
if (BO1 && BO1->getOpcode() == Instruction::Add) {
4651-
C = BO1->getOperand(0);
4652-
D = BO1->getOperand(1);
4658+
if (BO1) {
4659+
match(BO1, m_AddLike(m_Value(C), m_Value(D)));
4660+
NoOp1WrapProblem = hasNoWrapProblem(*BO1, Pred, Op1HasNSW, Op1HasNUW);
46534661
}
46544662

46554663
// icmp (A+B), A -> icmp B, 0 for equalities or if there is no overflow.
@@ -4769,17 +4777,15 @@ Instruction *InstCombinerImpl::foldICmpBinOp(ICmpInst &I,
47694777
APInt AP2Abs = AP2->abs();
47704778
if (AP1Abs.uge(AP2Abs)) {
47714779
APInt Diff = *AP1 - *AP2;
4772-
bool HasNUW = BO0->hasNoUnsignedWrap() && Diff.ule(*AP1);
4773-
bool HasNSW = BO0->hasNoSignedWrap();
47744780
Constant *C3 = Constant::getIntegerValue(BO0->getType(), Diff);
4775-
Value *NewAdd = Builder.CreateAdd(A, C3, "", HasNUW, HasNSW);
4781+
Value *NewAdd = Builder.CreateAdd(
4782+
A, C3, "", Op0HasNUW && Diff.ule(*AP1), Op0HasNSW);
47764783
return new ICmpInst(Pred, NewAdd, C);
47774784
} else {
47784785
APInt Diff = *AP2 - *AP1;
4779-
bool HasNUW = BO1->hasNoUnsignedWrap() && Diff.ule(*AP2);
4780-
bool HasNSW = BO1->hasNoSignedWrap();
47814786
Constant *C3 = Constant::getIntegerValue(BO0->getType(), Diff);
4782-
Value *NewAdd = Builder.CreateAdd(C, C3, "", HasNUW, HasNSW);
4787+
Value *NewAdd = Builder.CreateAdd(
4788+
C, C3, "", Op1HasNUW && Diff.ule(*AP2), Op1HasNSW);
47834789
return new ICmpInst(Pred, A, NewAdd);
47844790
}
47854791
}
@@ -4873,16 +4879,14 @@ Instruction *InstCombinerImpl::foldICmpBinOp(ICmpInst &I,
48734879
isKnownNonZero(Z, Q.DL, /*Depth=*/0, Q.AC, Q.CxtI, Q.DT);
48744880
// if Z != 0 and nsw(X * Z) and nsw(Y * Z)
48754881
// X * Z eq/ne Y * Z -> X eq/ne Y
4876-
if (NonZero && BO0 && BO1 && BO0->hasNoSignedWrap() &&
4877-
BO1->hasNoSignedWrap())
4882+
if (NonZero && BO0 && BO1 && Op0HasNSW && Op1HasNSW)
48784883
return new ICmpInst(Pred, X, Y);
48794884
} else
48804885
NonZero = isKnownNonZero(Z, Q.DL, /*Depth=*/0, Q.AC, Q.CxtI, Q.DT);
48814886

48824887
// If Z != 0 and nuw(X * Z) and nuw(Y * Z)
48834888
// X * Z u{lt/le/gt/ge}/eq/ne Y * Z -> X u{lt/le/gt/ge}/eq/ne Y
4884-
if (NonZero && BO0 && BO1 && BO0->hasNoUnsignedWrap() &&
4885-
BO1->hasNoUnsignedWrap())
4889+
if (NonZero && BO0 && BO1 && Op0HasNUW && Op1HasNUW)
48864890
return new ICmpInst(Pred, X, Y);
48874891
}
48884892
}
@@ -4982,8 +4986,8 @@ Instruction *InstCombinerImpl::foldICmpBinOp(ICmpInst &I,
49824986
return new ICmpInst(Pred, BO0->getOperand(0), BO1->getOperand(0));
49834987

49844988
case Instruction::Shl: {
4985-
bool NUW = BO0->hasNoUnsignedWrap() && BO1->hasNoUnsignedWrap();
4986-
bool NSW = BO0->hasNoSignedWrap() && BO1->hasNoSignedWrap();
4989+
bool NUW = Op0HasNUW && Op1HasNUW;
4990+
bool NSW = Op0HasNSW && Op1HasNSW;
49874991
if (!NUW && !NSW)
49884992
break;
49894993
if (!NSW && I.isSigned())

‎llvm/test/Transforms/InstCombine/icmp.ll

Lines changed: 149 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -3963,10 +3963,9 @@ define <8 x i1> @bitreverse_vec_ne(<8 x i16> %x, <8 x i16> %y) {
39633963
define i1 @knownbits1(i8 %a, i8 %b) {
39643964
; CHECK-LABEL: @knownbits1(
39653965
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], 1
3966-
; CHECK-NEXT: [[A2:%.*]] = or disjoint i8 [[A1]], 4
39673966
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3968-
; CHECK-NEXT: [[B2:%.*]] = or disjoint i8 [[B1]], 5
3969-
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A2]], [[B2]]
3967+
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1
3968+
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A1]], [[TMP1]]
39703969
; CHECK-NEXT: ret i1 [[C]]
39713970
;
39723971
%a1 = and i8 %a, 5
@@ -3980,10 +3979,9 @@ define i1 @knownbits1(i8 %a, i8 %b) {
39803979
define i1 @knownbits2(i8 %a, i8 %b) {
39813980
; CHECK-LABEL: @knownbits2(
39823981
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], 1
3983-
; CHECK-NEXT: [[A2:%.*]] = or disjoint i8 [[A1]], 4
39843982
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3985-
; CHECK-NEXT: [[B2:%.*]] = or disjoint i8 [[B1]], 5
3986-
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A2]], [[B2]]
3983+
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1
3984+
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A1]], [[TMP1]]
39873985
; CHECK-NEXT: ret i1 [[C]]
39883986
;
39893987
%a1 = and i8 %a, 5
@@ -3997,10 +3995,9 @@ define i1 @knownbits2(i8 %a, i8 %b) {
39973995
define i1 @knownbits3(i8 %a, i8 %b) {
39983996
; CHECK-LABEL: @knownbits3(
39993997
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], 1
4000-
; CHECK-NEXT: [[A2:%.*]] = or disjoint i8 [[A1]], 4
40013998
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
4002-
; CHECK-NEXT: [[B2:%.*]] = or disjoint i8 [[B1]], 5
4003-
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B2]], [[A2]]
3999+
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1
4000+
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[TMP1]], [[A1]]
40044001
; CHECK-NEXT: ret i1 [[C]]
40054002
;
40064003
%a1 = and i8 %a, 5
@@ -4014,10 +4011,9 @@ define i1 @knownbits3(i8 %a, i8 %b) {
40144011
define <2 x i1> @knownbits4(<2 x i8> %a, <2 x i8> %b) {
40154012
; CHECK-LABEL: @knownbits4(
40164013
; CHECK-NEXT: [[A1:%.*]] = and <2 x i8> [[A:%.*]], <i8 1, i8 1>
4017-
; CHECK-NEXT: [[A2:%.*]] = or disjoint <2 x i8> [[A1]], <i8 4, i8 4>
40184014
; CHECK-NEXT: [[B1:%.*]] = and <2 x i8> [[B:%.*]], <i8 2, i8 2>
4019-
; CHECK-NEXT: [[B2:%.*]] = or disjoint <2 x i8> [[B1]], <i8 5, i8 5>
4020-
; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i8> [[B2]], [[A2]]
4015+
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint <2 x i8> [[B1]], <i8 1, i8 1>
4016+
; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i8> [[TMP1]], [[A1]]
40214017
; CHECK-NEXT: ret <2 x i1> [[C]]
40224018
;
40234019
%a1 = and <2 x i8> %a, <i8 5, i8 5>
@@ -4033,10 +4029,9 @@ define <2 x i1> @knownbits4(<2 x i8> %a, <2 x i8> %b) {
40334029
define i1 @knownbits5(i8 %a, i8 %b) {
40344030
; CHECK-LABEL: @knownbits5(
40354031
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], -127
4036-
; CHECK-NEXT: [[A2:%.*]] = or disjoint i8 [[A1]], 4
40374032
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
4038-
; CHECK-NEXT: [[B2:%.*]] = or disjoint i8 [[B1]], 5
4039-
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A2]], [[B2]]
4033+
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1
4034+
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A1]], [[TMP1]]
40404035
; CHECK-NEXT: ret i1 [[C]]
40414036
;
40424037
%a1 = and i8 %a, 133
@@ -4050,10 +4045,9 @@ define i1 @knownbits5(i8 %a, i8 %b) {
40504045
define i1 @knownbits6(i8 %a, i8 %b) {
40514046
; CHECK-LABEL: @knownbits6(
40524047
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], -127
4053-
; CHECK-NEXT: [[A2:%.*]] = or disjoint i8 [[A1]], 4
40544048
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
4055-
; CHECK-NEXT: [[B2:%.*]] = or disjoint i8 [[B1]], 5
4056-
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A2]], [[B2]]
4049+
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1
4050+
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A1]], [[TMP1]]
40574051
; CHECK-NEXT: ret i1 [[C]]
40584052
;
40594053
%a1 = and i8 %a, 133
@@ -4067,10 +4061,9 @@ define i1 @knownbits6(i8 %a, i8 %b) {
40674061
define <2 x i1> @knownbits7(<2 x i8> %a, <2 x i8> %b) {
40684062
; CHECK-LABEL: @knownbits7(
40694063
; CHECK-NEXT: [[A1:%.*]] = and <2 x i8> [[A:%.*]], <i8 -127, i8 -127>
4070-
; CHECK-NEXT: [[A2:%.*]] = or disjoint <2 x i8> [[A1]], <i8 4, i8 4>
40714064
; CHECK-NEXT: [[B1:%.*]] = and <2 x i8> [[B:%.*]], <i8 2, i8 2>
4072-
; CHECK-NEXT: [[B2:%.*]] = or disjoint <2 x i8> [[B1]], <i8 5, i8 5>
4073-
; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i8> [[B2]], [[A2]]
4065+
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint <2 x i8> [[B1]], <i8 1, i8 1>
4066+
; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i8> [[TMP1]], [[A1]]
40744067
; CHECK-NEXT: ret <2 x i1> [[C]]
40754068
;
40764069
%a1 = and <2 x i8> %a, <i8 133, i8 133>
@@ -4084,10 +4077,9 @@ define <2 x i1> @knownbits7(<2 x i8> %a, <2 x i8> %b) {
40844077
define i1 @knownbits8(i8 %a, i8 %b) {
40854078
; CHECK-LABEL: @knownbits8(
40864079
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], -127
4087-
; CHECK-NEXT: [[A2:%.*]] = or disjoint i8 [[A1]], 4
40884080
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
4089-
; CHECK-NEXT: [[B2:%.*]] = or disjoint i8 [[B1]], 5
4090-
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[B2]], [[A2]]
4081+
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1
4082+
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[TMP1]], [[A1]]
40914083
; CHECK-NEXT: ret i1 [[C]]
40924084
;
40934085
%a1 = and i8 %a, 133
@@ -5013,3 +5005,136 @@ define i1 @or_positive_sgt_zero_multi_use(i8 %a) {
50135005
%cmp = icmp sgt i8 %b, 0
50145006
ret i1 %cmp
50155007
}
5008+
5009+
5010+
define i1 @disjoint_or_sgt_1(i8 %a, i8 %b) {
5011+
; CHECK-LABEL: @disjoint_or_sgt_1(
5012+
; CHECK-NEXT: [[B1:%.*]] = add nsw i8 [[B:%.*]], 2
5013+
; CHECK-NEXT: [[ICMP_:%.*]] = icmp sle i8 [[B1]], [[A:%.*]]
5014+
; CHECK-NEXT: ret i1 [[ICMP_]]
5015+
;
5016+
%a1 = or disjoint i8 %a, 1
5017+
%b1 = add nsw i8 %b, 2
5018+
%icmp_ = icmp sgt i8 %a1, %b1
5019+
ret i1 %icmp_
5020+
}
5021+
5022+
define i1 @disjoint_or_sgt_2(i8 %a, i8 %b) {
5023+
; CHECK-LABEL: @disjoint_or_sgt_2(
5024+
; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A:%.*]], 2
5025+
; CHECK-NEXT: [[B1:%.*]] = add i8 [[B:%.*]], 1
5026+
; CHECK-NEXT: [[ICMP_:%.*]] = icmp sgt i8 [[A1]], [[B1]]
5027+
; CHECK-NEXT: ret i1 [[ICMP_]]
5028+
;
5029+
%a1 = or disjoint i8 %a, 2
5030+
%b1 = add i8 %b, 1
5031+
%icmp_ = icmp sgt i8 %a1, %b1
5032+
ret i1 %icmp_
5033+
}
5034+
5035+
define i1 @disjoint_or_sgt_3(i8 %a, i8 %b) {
5036+
; CHECK-LABEL: @disjoint_or_sgt_3(
5037+
; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A:%.*]], 2
5038+
; CHECK-NEXT: [[B1:%.*]] = add nuw i8 [[B:%.*]], 1
5039+
; CHECK-NEXT: [[ICMP_:%.*]] = icmp sgt i8 [[A1]], [[B1]]
5040+
; CHECK-NEXT: ret i1 [[ICMP_]]
5041+
;
5042+
%a1 = or disjoint i8 %a, 2
5043+
%b1 = add nuw i8 %b, 1
5044+
%icmp_ = icmp sgt i8 %a1, %b1
5045+
ret i1 %icmp_
5046+
}
5047+
5048+
define i1 @disjoint_or_ugt_1(i8 %a, i8 %b) {
5049+
; CHECK-LABEL: @disjoint_or_ugt_1(
5050+
; CHECK-NEXT: [[B1:%.*]] = add nsw i8 [[B:%.*]], 2
5051+
; CHECK-NEXT: [[ICMP_:%.*]] = icmp ule i8 [[B1]], [[A:%.*]]
5052+
; CHECK-NEXT: ret i1 [[ICMP_]]
5053+
;
5054+
%a1 = or disjoint i8 %a, 1
5055+
%b1 = add nsw i8 %b, 2
5056+
%icmp_ = icmp ugt i8 %a1, %b1
5057+
ret i1 %icmp_
5058+
}
5059+
5060+
define i1 @disjoint_or_ugt_2(i8 %a, i8 %b) {
5061+
; CHECK-LABEL: @disjoint_or_ugt_2(
5062+
; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A:%.*]], 2
5063+
; CHECK-NEXT: [[B1:%.*]] = add i8 [[B:%.*]], 1
5064+
; CHECK-NEXT: [[ICMP_:%.*]] = icmp ugt i8 [[A1]], [[B1]]
5065+
; CHECK-NEXT: ret i1 [[ICMP_]]
5066+
;
5067+
%a1 = or disjoint i8 %a, 2
5068+
%b1 = add i8 %b, 1
5069+
%icmp_ = icmp ugt i8 %a1, %b1
5070+
ret i1 %icmp_
5071+
}
5072+
5073+
define i1 @disjoint_or_ugt_3(i8 %a, i8 %b) {
5074+
; CHECK-LABEL: @disjoint_or_ugt_3(
5075+
; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A:%.*]], 2
5076+
; CHECK-NEXT: [[B1:%.*]] = add nuw i8 [[B:%.*]], 1
5077+
; CHECK-NEXT: [[ICMP_:%.*]] = icmp ugt i8 [[A1]], [[B1]]
5078+
; CHECK-NEXT: ret i1 [[ICMP_]]
5079+
;
5080+
%a1 = or disjoint i8 %a, 2
5081+
%b1 = add nuw i8 %b, 1
5082+
%icmp_ = icmp ugt i8 %a1, %b1
5083+
ret i1 %icmp_
5084+
}
5085+
5086+
define i1 @deduce_nuw_flag_1(i8 %a, i8 %b) {
5087+
; CHECK-LABEL: @deduce_nuw_flag_1(
5088+
; CHECK-NEXT: entry:
5089+
; CHECK-NEXT: [[TMP0:%.*]] = add nuw i8 [[B:%.*]], 1
5090+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP0]], [[A:%.*]]
5091+
; CHECK-NEXT: ret i1 [[CMP]]
5092+
;
5093+
entry:
5094+
%add1 = add nuw i8 %b, 2
5095+
%add2 = add i8 %a, 1
5096+
%cmp = icmp eq i8 %add1, %add2
5097+
ret i1 %cmp
5098+
}
5099+
5100+
define i1 @deduce_nuw_flag_2(i8 %a, i8 %b) {
5101+
; CHECK-LABEL: @deduce_nuw_flag_2(
5102+
; CHECK-NEXT: entry:
5103+
; CHECK-NEXT: [[TMP0:%.*]] = add nuw i8 [[B:%.*]], 1
5104+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP0]], [[A:%.*]]
5105+
; CHECK-NEXT: ret i1 [[CMP]]
5106+
;
5107+
entry:
5108+
%add1 = add nuw i8 %b, 2
5109+
%add2 = add i8 %a, 1
5110+
%cmp = icmp eq i8 %add2, %add1
5111+
ret i1 %cmp
5112+
}
5113+
5114+
define i1 @dont_deduce_nuw_flag_1(i8 %a, i8 %b) {
5115+
; CHECK-LABEL: @dont_deduce_nuw_flag_1(
5116+
; CHECK-NEXT: entry:
5117+
; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[B:%.*]], -1
5118+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP0]], [[A:%.*]]
5119+
; CHECK-NEXT: ret i1 [[CMP]]
5120+
;
5121+
entry:
5122+
%add1 = add nuw i8 %b, -2
5123+
%add2 = add i8 %a, -1
5124+
%cmp = icmp eq i8 %add1, %add2
5125+
ret i1 %cmp
5126+
}
5127+
5128+
define i1 @dont_deduce_nuw_flag_2(i8 %a, i8 %b) {
5129+
; CHECK-LABEL: @dont_deduce_nuw_flag_2(
5130+
; CHECK-NEXT: entry:
5131+
; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[B:%.*]], -1
5132+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP0]], [[A:%.*]]
5133+
; CHECK-NEXT: ret i1 [[CMP]]
5134+
;
5135+
entry:
5136+
%add1 = add nuw i8 %b, -2
5137+
%add2 = add i8 %a, -1
5138+
%cmp = icmp eq i8 %add2, %add1
5139+
ret i1 %cmp
5140+
}

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