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use auto with dyn_casted values; NFC
llvm-svn: 256579
1 parent 2d82f91 commit 7a7abc9

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+9
-11
lines changed

1 file changed

+9
-11
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llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1281,7 +1281,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
12811281
isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
12821282
return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
12831283

1284-
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1284+
if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
12851285
const APInt &C1 = N1C->getAPIntValue();
12861286

12871287
// If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
@@ -1346,7 +1346,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
13461346
PreExt = N0->getOperand(0);
13471347
} else if (N0->getOpcode() == ISD::AND) {
13481348
// DAGCombine turns costly ZExts into ANDs
1349-
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1349+
if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
13501350
if ((C->getAPIntValue()+1).isPowerOf2()) {
13511351
MinBits = C->getAPIntValue().countTrailingOnes();
13521352
PreExt = N0->getOperand(0);
@@ -1356,7 +1356,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
13561356
MinBits = N0->getOperand(0).getValueSizeInBits();
13571357
PreExt = N0->getOperand(0);
13581358
Signed = true;
1359-
} else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1359+
} else if (auto *LN0 = dyn_cast<LoadSDNode>(N0)) {
13601360
// ZEXTLOAD / SEXTLOAD
13611361
if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
13621362
MinBits = LN0->getMemoryVT().getSizeInBits();
@@ -1708,8 +1708,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
17081708
(isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
17091709
N0.getOpcode() == ISD::AND) {
17101710
auto &DL = DAG.getDataLayout();
1711-
if (ConstantSDNode *AndRHS =
1712-
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1711+
if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
17131712
EVT ShiftTy = DCI.isBeforeLegalize()
17141713
? getPointerTy(DL)
17151714
: getShiftAmountTy(N0.getValueType(), DL);
@@ -1739,8 +1738,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
17391738
// (X & -256) == 256 -> (X >> 8) == 1
17401739
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
17411740
N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1742-
if (ConstantSDNode *AndRHS =
1743-
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1741+
if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
17441742
const APInt &AndRHSC = AndRHS->getAPIntValue();
17451743
if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
17461744
unsigned ShiftBits = AndRHSC.countTrailingZeros();
@@ -1794,7 +1792,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
17941792
// Constant fold or commute setcc.
17951793
SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
17961794
if (O.getNode()) return O;
1797-
} else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1795+
} else if (auto *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
17981796
// If the RHS of an FP comparison is a constant, simplify it away in
17991797
// some cases.
18001798
if (CFP->getValueAPF().isNaN()) {
@@ -1911,8 +1909,8 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
19111909
// to be careful about increasing register pressure needlessly.
19121910
bool LegalRHSImm = false;
19131911

1914-
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1915-
if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1912+
if (auto *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1913+
if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
19161914
// Turn (X+C1) == C2 --> X == C2-C1
19171915
if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
19181916
return DAG.getSetCC(dl, VT, N0.getOperand(0),
@@ -1935,7 +1933,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
19351933
}
19361934

19371935
// Turn (C1-X) == C2 --> X == C1-C2
1938-
if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1936+
if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
19391937
if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
19401938
return
19411939
DAG.getSetCC(dl, VT, N0.getOperand(1),

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