@@ -1281,7 +1281,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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isCondCodeLegal (SwappedCC, N0.getSimpleValueType ())))
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return DAG.getSetCC (dl, VT, N1, N0, SwappedCC);
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- if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode ())) {
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+ if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode ())) {
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const APInt &C1 = N1C->getAPIntValue ();
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// If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
@@ -1346,7 +1346,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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PreExt = N0->getOperand (0 );
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} else if (N0->getOpcode () == ISD::AND) {
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// DAGCombine turns costly ZExts into ANDs
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- if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand (1 )))
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+ if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand (1 )))
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if ((C->getAPIntValue ()+1 ).isPowerOf2 ()) {
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MinBits = C->getAPIntValue ().countTrailingOnes ();
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PreExt = N0->getOperand (0 );
@@ -1356,7 +1356,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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MinBits = N0->getOperand (0 ).getValueSizeInBits ();
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PreExt = N0->getOperand (0 );
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Signed = true ;
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- } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
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+ } else if (auto *LN0 = dyn_cast<LoadSDNode>(N0)) {
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// ZEXTLOAD / SEXTLOAD
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if (LN0->getExtensionType () == ISD::ZEXTLOAD) {
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MinBits = LN0->getMemoryVT ().getSizeInBits ();
@@ -1708,8 +1708,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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(isTypeLegal (VT) && VT.bitsLE (N0.getValueType ()))) &&
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N0.getOpcode () == ISD::AND) {
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auto &DL = DAG.getDataLayout ();
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- if (ConstantSDNode *AndRHS =
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- dyn_cast<ConstantSDNode>(N0.getOperand (1 ))) {
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+ if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand (1 ))) {
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EVT ShiftTy = DCI.isBeforeLegalize ()
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? getPointerTy (DL)
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: getShiftAmountTy (N0.getValueType (), DL);
@@ -1739,8 +1738,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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// (X & -256) == 256 -> (X >> 8) == 1
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if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
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N0.getOpcode () == ISD::AND && N0.hasOneUse ()) {
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- if (ConstantSDNode *AndRHS =
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- dyn_cast<ConstantSDNode>(N0.getOperand (1 ))) {
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+ if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand (1 ))) {
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const APInt &AndRHSC = AndRHS->getAPIntValue ();
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if ((-AndRHSC).isPowerOf2 () && (AndRHSC & C1) == C1) {
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unsigned ShiftBits = AndRHSC.countTrailingZeros ();
@@ -1794,7 +1792,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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// Constant fold or commute setcc.
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SDValue O = DAG.FoldSetCC (VT, N0, N1, Cond, dl);
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if (O.getNode ()) return O;
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- } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode ())) {
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+ } else if (auto *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode ())) {
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// If the RHS of an FP comparison is a constant, simplify it away in
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// some cases.
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if (CFP->getValueAPF ().isNaN ()) {
@@ -1911,8 +1909,8 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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// to be careful about increasing register pressure needlessly.
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bool LegalRHSImm = false ;
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- if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
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- if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand (1 ))) {
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+ if (auto *RHSC = dyn_cast<ConstantSDNode>(N1)) {
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+ if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand (1 ))) {
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// Turn (X+C1) == C2 --> X == C2-C1
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if (N0.getOpcode () == ISD::ADD && N0.getNode ()->hasOneUse ()) {
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return DAG.getSetCC (dl, VT, N0.getOperand (0 ),
@@ -1935,7 +1933,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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}
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// Turn (C1-X) == C2 --> X == C1-C2
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- if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand (0 ))) {
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+ if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand (0 ))) {
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if (N0.getOpcode () == ISD::SUB && N0.getNode ()->hasOneUse ()) {
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return
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DAG.getSetCC (dl, VT, N0.getOperand (1 ),
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