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kmclaughlin-armkmclaughlin-arm
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- Enable subreg liveness in sme2-intrinsics-qcvt.ll
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‎llvm/test/CodeGen/AArch64/sme2-intrinsics-qcvt.ll

Lines changed: 23 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming -enable-subreg-liveness -verify-machineinstrs < %s | FileCheck %s
33

44
;
55
; SQCVT
@@ -48,21 +48,17 @@ define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
4848
; CHECK-LABEL: multi_vector_qcvt_x4_s16_s64_tuple:
4949
; CHECK: // %bb.0: // %entry
5050
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
51-
; CHECK-NEXT: addvl sp, sp, #-13
51+
; CHECK-NEXT: addvl sp, sp, #-9
5252
; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Folded Spill
53-
; CHECK-NEXT: str z19, [sp, #1, mul vl] // 16-byte Folded Spill
54-
; CHECK-NEXT: str z18, [sp, #2, mul vl] // 16-byte Folded Spill
55-
; CHECK-NEXT: str z17, [sp, #3, mul vl] // 16-byte Folded Spill
56-
; CHECK-NEXT: str z16, [sp, #4, mul vl] // 16-byte Folded Spill
57-
; CHECK-NEXT: str z15, [sp, #5, mul vl] // 16-byte Folded Spill
58-
; CHECK-NEXT: str z14, [sp, #6, mul vl] // 16-byte Folded Spill
59-
; CHECK-NEXT: str z13, [sp, #7, mul vl] // 16-byte Folded Spill
60-
; CHECK-NEXT: str z12, [sp, #8, mul vl] // 16-byte Folded Spill
61-
; CHECK-NEXT: str z11, [sp, #9, mul vl] // 16-byte Folded Spill
62-
; CHECK-NEXT: str z10, [sp, #10, mul vl] // 16-byte Folded Spill
63-
; CHECK-NEXT: str z9, [sp, #11, mul vl] // 16-byte Folded Spill
64-
; CHECK-NEXT: str z8, [sp, #12, mul vl] // 16-byte Folded Spill
65-
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xe8, 0x00, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 104 * VG
53+
; CHECK-NEXT: str z15, [sp, #1, mul vl] // 16-byte Folded Spill
54+
; CHECK-NEXT: str z14, [sp, #2, mul vl] // 16-byte Folded Spill
55+
; CHECK-NEXT: str z13, [sp, #3, mul vl] // 16-byte Folded Spill
56+
; CHECK-NEXT: str z12, [sp, #4, mul vl] // 16-byte Folded Spill
57+
; CHECK-NEXT: str z11, [sp, #5, mul vl] // 16-byte Folded Spill
58+
; CHECK-NEXT: str z10, [sp, #6, mul vl] // 16-byte Folded Spill
59+
; CHECK-NEXT: str z9, [sp, #7, mul vl] // 16-byte Folded Spill
60+
; CHECK-NEXT: str z8, [sp, #8, mul vl] // 16-byte Folded Spill
61+
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc8, 0x00, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 72 * VG
6662
; CHECK-NEXT: .cfi_offset w29, -16
6763
; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG
6864
; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x70, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d9 @ cfa - 16 - 16 * VG
@@ -81,36 +77,20 @@ define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
8177
; CHECK-NEXT: add x8, x9, x8
8278
; CHECK-NEXT: ld1d { z2.d, z6.d, z10.d, z14.d }, pn8/z, [x10]
8379
; CHECK-NEXT: ld1d { z3.d, z7.d, z11.d, z15.d }, pn8/z, [x8]
84-
; CHECK-NEXT: mov z24.d, z0.d
85-
; CHECK-NEXT: mov z25.d, z1.d
86-
; CHECK-NEXT: mov z28.d, z4.d
87-
; CHECK-NEXT: mov z29.d, z5.d
88-
; CHECK-NEXT: mov z16.d, z8.d
89-
; CHECK-NEXT: mov z17.d, z9.d
90-
; CHECK-NEXT: mov z26.d, z2.d
91-
; CHECK-NEXT: mov z27.d, z3.d
92-
; CHECK-NEXT: mov z30.d, z6.d
93-
; CHECK-NEXT: mov z31.d, z7.d
94-
; CHECK-NEXT: mov z18.d, z10.d
95-
; CHECK-NEXT: mov z19.d, z11.d
96-
; CHECK-NEXT: sqcvt z0.h, { z24.d - z27.d }
97-
; CHECK-NEXT: sqcvt z1.h, { z28.d - z31.d }
98-
; CHECK-NEXT: sqcvt z2.h, { z16.d - z19.d }
80+
; CHECK-NEXT: sqcvt z0.h, { z0.d - z3.d }
81+
; CHECK-NEXT: sqcvt z1.h, { z4.d - z7.d }
82+
; CHECK-NEXT: sqcvt z2.h, { z8.d - z11.d }
9983
; CHECK-NEXT: sqcvt z3.h, { z12.d - z15.d }
100-
; CHECK-NEXT: ldr z19, [sp, #1, mul vl] // 16-byte Folded Reload
101-
; CHECK-NEXT: ldr z18, [sp, #2, mul vl] // 16-byte Folded Reload
102-
; CHECK-NEXT: ldr z17, [sp, #3, mul vl] // 16-byte Folded Reload
103-
; CHECK-NEXT: ldr z16, [sp, #4, mul vl] // 16-byte Folded Reload
104-
; CHECK-NEXT: ldr z15, [sp, #5, mul vl] // 16-byte Folded Reload
105-
; CHECK-NEXT: ldr z14, [sp, #6, mul vl] // 16-byte Folded Reload
106-
; CHECK-NEXT: ldr z13, [sp, #7, mul vl] // 16-byte Folded Reload
107-
; CHECK-NEXT: ldr z12, [sp, #8, mul vl] // 16-byte Folded Reload
108-
; CHECK-NEXT: ldr z11, [sp, #9, mul vl] // 16-byte Folded Reload
109-
; CHECK-NEXT: ldr z10, [sp, #10, mul vl] // 16-byte Folded Reload
110-
; CHECK-NEXT: ldr z9, [sp, #11, mul vl] // 16-byte Folded Reload
111-
; CHECK-NEXT: ldr z8, [sp, #12, mul vl] // 16-byte Folded Reload
84+
; CHECK-NEXT: ldr z15, [sp, #1, mul vl] // 16-byte Folded Reload
85+
; CHECK-NEXT: ldr z14, [sp, #2, mul vl] // 16-byte Folded Reload
86+
; CHECK-NEXT: ldr z13, [sp, #3, mul vl] // 16-byte Folded Reload
87+
; CHECK-NEXT: ldr z12, [sp, #4, mul vl] // 16-byte Folded Reload
88+
; CHECK-NEXT: ldr z11, [sp, #5, mul vl] // 16-byte Folded Reload
89+
; CHECK-NEXT: ldr z10, [sp, #6, mul vl] // 16-byte Folded Reload
90+
; CHECK-NEXT: ldr z9, [sp, #7, mul vl] // 16-byte Folded Reload
91+
; CHECK-NEXT: ldr z8, [sp, #8, mul vl] // 16-byte Folded Reload
11292
; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Folded Reload
113-
; CHECK-NEXT: addvl sp, sp, #13
93+
; CHECK-NEXT: addvl sp, sp, #9
11494
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
11595
; CHECK-NEXT: ret
11696
entry:

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