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1 parent 43bc584 commit 7a86645Copy full SHA for 7a86645
llvm/lib/Target/VE/VETargetTransformInfo.h
@@ -64,6 +64,14 @@ class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
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llvm_unreachable("Unsupported register kind");
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}
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+ /// \returns How the target needs this vector-predicated operation to be
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+ /// transformed.
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+ TargetTransformInfo::VPLegalization
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+ getVPLegalizationStrategy(const VPIntrinsic &PI) const {
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+ using VPLegalization = TargetTransformInfo::VPLegalization;
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+ return VPLegalization(VPLegalization::Legal, VPLegalization::Legal);
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+ }
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+
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unsigned getMinVectorRegisterBitWidth() const {
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// TODO report vregs once vector isel is stable.
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return 0;
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