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michaelmaitlandmichaelmaitland
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fixup! add more tests
1 parent c585712 commit 7ac9ecb

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4 files changed

+1198
-2
lines changed

4 files changed

+1198
-2
lines changed

‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3303,8 +3303,14 @@ bool IRTranslator::translateShuffleVector(const User &U,
33033303
// poison are treated as zeroinitializer here).
33043304
if (U.getOperand(0)->getType()->isScalableTy()) {
33053305
Register Val = getOrCreateVReg(*U.getOperand(0));
3306-
auto SplatVal = MIRBuilder.buildExtractVectorElementConstant(
3307-
MRI->getType(Val).getElementType(), Val, 0);
3306+
// We don't use buildExtractVectorElementConstant because it creates
3307+
// problems for CSE since the constant gets placed in a different basic
3308+
// block.
3309+
unsigned VecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
3310+
auto *IdxCI = ConstantInt::get(U.getContext(), APInt(VecIdxWidth, 0));
3311+
Register Idx = getOrCreateVReg(*IdxCI);
3312+
auto SplatVal = MIRBuilder.buildExtractVectorElement(
3313+
MRI->getType(Val).getElementType(), Val, Idx);
33083314
MIRBuilder.buildSplatVector(getOrCreateVReg(U), SplatVal);
33093315
return true;
33103316
}

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/splatvector-rv32.mir

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ body: |
1010
; CHECK-LABEL: name: splat_zero_nxv1i8
1111
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
1212
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
13+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
1314
; CHECK-NEXT: [[PseudoVMV_V_X_MF8_:%[0-9]+]]:vr = PseudoVMV_V_X_MF8 [[DEF]], [[COPY]], -1, 3 /* e8 */, 0 /* tu, mu */
1415
; CHECK-NEXT: $v8 = COPY [[PseudoVMV_V_X_MF8_]]
1516
; CHECK-NEXT: PseudoRET implicit $v8
@@ -28,6 +29,7 @@ body: |
2829
; CHECK-LABEL: name: splat_zero_nxv2i8
2930
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
3031
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
32+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
3133
; CHECK-NEXT: [[PseudoVMV_V_X_MF4_:%[0-9]+]]:vr = PseudoVMV_V_X_MF4 [[DEF]], [[COPY]], -1, 3 /* e8 */, 0 /* tu, mu */
3234
; CHECK-NEXT: $v8 = COPY [[PseudoVMV_V_X_MF4_]]
3335
; CHECK-NEXT: PseudoRET implicit $v8
@@ -46,6 +48,7 @@ body: |
4648
; CHECK-LABEL: name: splat_zero_nxv4i8
4749
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
4850
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
51+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
4952
; CHECK-NEXT: [[PseudoVMV_V_X_MF2_:%[0-9]+]]:vr = PseudoVMV_V_X_MF2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 0 /* tu, mu */
5053
; CHECK-NEXT: $v8 = COPY [[PseudoVMV_V_X_MF2_]]
5154
; CHECK-NEXT: PseudoRET implicit $v8
@@ -64,6 +67,7 @@ body: |
6467
; CHECK-LABEL: name: splat_zero_nxv8i8
6568
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
6669
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
70+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
6771
; CHECK-NEXT: [[PseudoVMV_V_X_M1_:%[0-9]+]]:vr = PseudoVMV_V_X_M1 [[DEF]], [[COPY]], -1, 3 /* e8 */, 0 /* tu, mu */
6872
; CHECK-NEXT: $v8 = COPY [[PseudoVMV_V_X_M1_]]
6973
; CHECK-NEXT: PseudoRET implicit $v8
@@ -82,6 +86,7 @@ body: |
8286
; CHECK-LABEL: name: splat_zero_nxv16i8
8387
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
8488
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
89+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
8590
; CHECK-NEXT: [[PseudoVMV_V_X_M2_:%[0-9]+]]:vrm2 = PseudoVMV_V_X_M2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 0 /* tu, mu */
8691
; CHECK-NEXT: $v8m2 = COPY [[PseudoVMV_V_X_M2_]]
8792
; CHECK-NEXT: PseudoRET implicit $v8m2
@@ -100,6 +105,7 @@ body: |
100105
; CHECK-LABEL: name: splat_zero_nxv32i8
101106
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
102107
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
108+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
103109
; CHECK-NEXT: [[PseudoVMV_V_X_M4_:%[0-9]+]]:vrm4 = PseudoVMV_V_X_M4 [[DEF]], [[COPY]], -1, 3 /* e8 */, 0 /* tu, mu */
104110
; CHECK-NEXT: $v8m4 = COPY [[PseudoVMV_V_X_M4_]]
105111
; CHECK-NEXT: PseudoRET implicit $v8m4
@@ -118,6 +124,7 @@ body: |
118124
; CHECK-LABEL: name: splat_zero_nxv64i8
119125
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
120126
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
127+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
121128
; CHECK-NEXT: [[PseudoVMV_V_X_M8_:%[0-9]+]]:vrm8 = PseudoVMV_V_X_M8 [[DEF]], [[COPY]], -1, 3 /* e8 */, 0 /* tu, mu */
122129
; CHECK-NEXT: $v8m8 = COPY [[PseudoVMV_V_X_M8_]]
123130
; CHECK-NEXT: PseudoRET implicit $v8m8
@@ -136,6 +143,7 @@ body: |
136143
; CHECK-LABEL: name: splat_zero_nxv1i16
137144
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
138145
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
146+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
139147
; CHECK-NEXT: [[PseudoVMV_V_X_MF4_:%[0-9]+]]:vr = PseudoVMV_V_X_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 0 /* tu, mu */
140148
; CHECK-NEXT: $v8 = COPY [[PseudoVMV_V_X_MF4_]]
141149
; CHECK-NEXT: PseudoRET implicit $v8
@@ -154,6 +162,7 @@ body: |
154162
; CHECK-LABEL: name: splat_zero_nxv2i16
155163
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
156164
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
165+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
157166
; CHECK-NEXT: [[PseudoVMV_V_X_MF2_:%[0-9]+]]:vr = PseudoVMV_V_X_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 0 /* tu, mu */
158167
; CHECK-NEXT: $v8 = COPY [[PseudoVMV_V_X_MF2_]]
159168
; CHECK-NEXT: PseudoRET implicit $v8
@@ -172,6 +181,7 @@ body: |
172181
; CHECK-LABEL: name: splat_zero_nxv4i16
173182
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
174183
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
184+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
175185
; CHECK-NEXT: [[PseudoVMV_V_X_M1_:%[0-9]+]]:vr = PseudoVMV_V_X_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 0 /* tu, mu */
176186
; CHECK-NEXT: $v8 = COPY [[PseudoVMV_V_X_M1_]]
177187
; CHECK-NEXT: PseudoRET implicit $v8
@@ -190,6 +200,7 @@ body: |
190200
; CHECK-LABEL: name: splat_zero_nxv8i16
191201
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
192202
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
203+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
193204
; CHECK-NEXT: [[PseudoVMV_V_X_M2_:%[0-9]+]]:vrm2 = PseudoVMV_V_X_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 0 /* tu, mu */
194205
; CHECK-NEXT: $v8m2 = COPY [[PseudoVMV_V_X_M2_]]
195206
; CHECK-NEXT: PseudoRET implicit $v8m2
@@ -208,6 +219,7 @@ body: |
208219
; CHECK-LABEL: name: splat_zero_nxv16i16
209220
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
210221
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
222+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
211223
; CHECK-NEXT: [[PseudoVMV_V_X_M4_:%[0-9]+]]:vrm4 = PseudoVMV_V_X_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 0 /* tu, mu */
212224
; CHECK-NEXT: $v8m4 = COPY [[PseudoVMV_V_X_M4_]]
213225
; CHECK-NEXT: PseudoRET implicit $v8m4
@@ -226,6 +238,7 @@ body: |
226238
; CHECK-LABEL: name: splat_zero_nxv32i16
227239
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
228240
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
241+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
229242
; CHECK-NEXT: [[PseudoVMV_V_X_M8_:%[0-9]+]]:vrm8 = PseudoVMV_V_X_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 0 /* tu, mu */
230243
; CHECK-NEXT: $v8m8 = COPY [[PseudoVMV_V_X_M8_]]
231244
; CHECK-NEXT: PseudoRET implicit $v8m8
@@ -244,6 +257,7 @@ body: |
244257
; CHECK-LABEL: name: splat_zero_nxv1i32
245258
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
246259
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
260+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
247261
; CHECK-NEXT: [[PseudoVMV_V_X_MF2_:%[0-9]+]]:vr = PseudoVMV_V_X_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 0 /* tu, mu */
248262
; CHECK-NEXT: $v8 = COPY [[PseudoVMV_V_X_MF2_]]
249263
; CHECK-NEXT: PseudoRET implicit $v8
@@ -262,6 +276,7 @@ body: |
262276
; CHECK-LABEL: name: splat_zero_nxv2i32
263277
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
264278
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
279+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
265280
; CHECK-NEXT: [[PseudoVMV_V_X_M1_:%[0-9]+]]:vr = PseudoVMV_V_X_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 0 /* tu, mu */
266281
; CHECK-NEXT: $v8 = COPY [[PseudoVMV_V_X_M1_]]
267282
; CHECK-NEXT: PseudoRET implicit $v8
@@ -280,6 +295,7 @@ body: |
280295
; CHECK-LABEL: name: splat_zero_nxv4i32
281296
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
282297
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
298+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
283299
; CHECK-NEXT: [[PseudoVMV_V_X_M2_:%[0-9]+]]:vrm2 = PseudoVMV_V_X_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 0 /* tu, mu */
284300
; CHECK-NEXT: $v8m2 = COPY [[PseudoVMV_V_X_M2_]]
285301
; CHECK-NEXT: PseudoRET implicit $v8m2
@@ -298,6 +314,7 @@ body: |
298314
; CHECK-LABEL: name: splat_zero_nxv8i32
299315
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
300316
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
317+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
301318
; CHECK-NEXT: [[PseudoVMV_V_X_M4_:%[0-9]+]]:vrm4 = PseudoVMV_V_X_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 0 /* tu, mu */
302319
; CHECK-NEXT: $v8m4 = COPY [[PseudoVMV_V_X_M4_]]
303320
; CHECK-NEXT: PseudoRET implicit $v8m4
@@ -316,6 +333,7 @@ body: |
316333
; CHECK-LABEL: name: splat_zero_nxv16i32
317334
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x0
318335
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
336+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
319337
; CHECK-NEXT: [[PseudoVMV_V_X_M8_:%[0-9]+]]:vrm8 = PseudoVMV_V_X_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 0 /* tu, mu */
320338
; CHECK-NEXT: $v8m8 = COPY [[PseudoVMV_V_X_M8_]]
321339
; CHECK-NEXT: PseudoRET implicit $v8m8
@@ -336,6 +354,7 @@ body: |
336354
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
337355
; CHECK-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY]], [[COPY1]]
338356
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
357+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
339358
; CHECK-NEXT: [[PseudoVFMV_V_FPR64_M1_:%[0-9]+]]:vr = PseudoVFMV_V_FPR64_M1 [[DEF]], [[BuildPairF64Pseudo]], -1, 6 /* e64 */, 0 /* tu, mu */
340359
; CHECK-NEXT: $v8 = COPY [[PseudoVFMV_V_FPR64_M1_]]
341360
; CHECK-NEXT: PseudoRET implicit $v8
@@ -358,6 +377,7 @@ body: |
358377
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
359378
; CHECK-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY]], [[COPY1]]
360379
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
380+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
361381
; CHECK-NEXT: [[PseudoVFMV_V_FPR64_M2_:%[0-9]+]]:vrm2 = PseudoVFMV_V_FPR64_M2 [[DEF]], [[BuildPairF64Pseudo]], -1, 6 /* e64 */, 0 /* tu, mu */
362382
; CHECK-NEXT: $v8m2 = COPY [[PseudoVFMV_V_FPR64_M2_]]
363383
; CHECK-NEXT: PseudoRET implicit $v8m2
@@ -380,6 +400,7 @@ body: |
380400
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
381401
; CHECK-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY]], [[COPY1]]
382402
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
403+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
383404
; CHECK-NEXT: [[PseudoVFMV_V_FPR64_M4_:%[0-9]+]]:vrm4 = PseudoVFMV_V_FPR64_M4 [[DEF]], [[BuildPairF64Pseudo]], -1, 6 /* e64 */, 0 /* tu, mu */
384405
; CHECK-NEXT: $v8m4 = COPY [[PseudoVFMV_V_FPR64_M4_]]
385406
; CHECK-NEXT: PseudoRET implicit $v8m4
@@ -402,6 +423,7 @@ body: |
402423
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
403424
; CHECK-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY]], [[COPY1]]
404425
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
426+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
405427
; CHECK-NEXT: [[PseudoVFMV_V_FPR64_M8_:%[0-9]+]]:vrm8 = PseudoVFMV_V_FPR64_M8 [[DEF]], [[BuildPairF64Pseudo]], -1, 6 /* e64 */, 0 /* tu, mu */
406428
; CHECK-NEXT: $v8m8 = COPY [[PseudoVFMV_V_FPR64_M8_]]
407429
; CHECK-NEXT: PseudoRET implicit $v8m8
@@ -424,6 +446,7 @@ body: |
424446
; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[COPY]]
425447
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[FMV_W_X]]
426448
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
449+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
427450
; CHECK-NEXT: [[PseudoVMV_V_X_MF2_:%[0-9]+]]:vr = PseudoVMV_V_X_MF2 [[DEF]], [[COPY1]], -1, 5 /* e32 */, 0 /* tu, mu */
428451
; CHECK-NEXT: $v8 = COPY [[PseudoVMV_V_X_MF2_]]
429452
; CHECK-NEXT: PseudoRET implicit $v8
@@ -445,6 +468,7 @@ body: |
445468
; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[COPY]]
446469
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[FMV_W_X]]
447470
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
471+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
448472
; CHECK-NEXT: [[PseudoVMV_V_X_M1_:%[0-9]+]]:vr = PseudoVMV_V_X_M1 [[DEF]], [[COPY1]], -1, 5 /* e32 */, 0 /* tu, mu */
449473
; CHECK-NEXT: $v8 = COPY [[PseudoVMV_V_X_M1_]]
450474
; CHECK-NEXT: PseudoRET implicit $v8
@@ -466,6 +490,7 @@ body: |
466490
; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[COPY]]
467491
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[FMV_W_X]]
468492
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
493+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
469494
; CHECK-NEXT: [[PseudoVMV_V_X_M2_:%[0-9]+]]:vrm2 = PseudoVMV_V_X_M2 [[DEF]], [[COPY1]], -1, 5 /* e32 */, 0 /* tu, mu */
470495
; CHECK-NEXT: $v8m2 = COPY [[PseudoVMV_V_X_M2_]]
471496
; CHECK-NEXT: PseudoRET implicit $v8m2
@@ -487,6 +512,7 @@ body: |
487512
; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[COPY]]
488513
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[FMV_W_X]]
489514
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
515+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
490516
; CHECK-NEXT: [[PseudoVMV_V_X_M4_:%[0-9]+]]:vrm4 = PseudoVMV_V_X_M4 [[DEF]], [[COPY1]], -1, 5 /* e32 */, 0 /* tu, mu */
491517
; CHECK-NEXT: $v8m4 = COPY [[PseudoVMV_V_X_M4_]]
492518
; CHECK-NEXT: PseudoRET implicit $v8m4
@@ -508,6 +534,7 @@ body: |
508534
; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[COPY]]
509535
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[FMV_W_X]]
510536
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
537+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
511538
; CHECK-NEXT: [[PseudoVMV_V_X_M8_:%[0-9]+]]:vrm8 = PseudoVMV_V_X_M8 [[DEF]], [[COPY1]], -1, 5 /* e32 */, 0 /* tu, mu */
512539
; CHECK-NEXT: $v8m8 = COPY [[PseudoVMV_V_X_M8_]]
513540
; CHECK-NEXT: PseudoRET implicit $v8m8
@@ -529,6 +556,7 @@ body: |
529556
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
530557
; CHECK-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY1]], [[COPY]]
531558
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
559+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
532560
; CHECK-NEXT: [[PseudoVFMV_V_FPR64_M1_:%[0-9]+]]:vr = PseudoVFMV_V_FPR64_M1 [[DEF]], [[BuildPairF64Pseudo]], -1, 6 /* e64 */, 0 /* tu, mu */
533561
; CHECK-NEXT: $v8 = COPY [[PseudoVFMV_V_FPR64_M1_]]
534562
; CHECK-NEXT: PseudoRET implicit $v8
@@ -549,6 +577,7 @@ body: |
549577
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
550578
; CHECK-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY1]], [[COPY]]
551579
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
580+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
552581
; CHECK-NEXT: [[PseudoVFMV_V_FPR64_M2_:%[0-9]+]]:vrm2 = PseudoVFMV_V_FPR64_M2 [[DEF]], [[BuildPairF64Pseudo]], -1, 6 /* e64 */, 0 /* tu, mu */
553582
; CHECK-NEXT: $v8m2 = COPY [[PseudoVFMV_V_FPR64_M2_]]
554583
; CHECK-NEXT: PseudoRET implicit $v8m2
@@ -569,6 +598,7 @@ body: |
569598
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
570599
; CHECK-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY1]], [[COPY]]
571600
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
601+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
572602
; CHECK-NEXT: [[PseudoVFMV_V_FPR64_M4_:%[0-9]+]]:vrm4 = PseudoVFMV_V_FPR64_M4 [[DEF]], [[BuildPairF64Pseudo]], -1, 6 /* e64 */, 0 /* tu, mu */
573603
; CHECK-NEXT: $v8m4 = COPY [[PseudoVFMV_V_FPR64_M4_]]
574604
; CHECK-NEXT: PseudoRET implicit $v8m4
@@ -589,6 +619,7 @@ body: |
589619
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
590620
; CHECK-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY1]], [[COPY]]
591621
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
622+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
592623
; CHECK-NEXT: [[PseudoVFMV_V_FPR64_M8_:%[0-9]+]]:vrm8 = PseudoVFMV_V_FPR64_M8 [[DEF]], [[BuildPairF64Pseudo]], -1, 6 /* e64 */, 0 /* tu, mu */
593624
; CHECK-NEXT: $v8m8 = COPY [[PseudoVFMV_V_FPR64_M8_]]
594625
; CHECK-NEXT: PseudoRET implicit $v8m8

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