Skip to content

Commit 7aeb7f4

Browse files
NexMingNexMing
committed
[RISCV][NFC] Fix a bug where AVL is the last MI in MBB.
1 parent bb00fd0 commit 7aeb7f4

File tree

2 files changed

+75
-7
lines changed

2 files changed

+75
-7
lines changed

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1119,25 +1119,26 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
11191119
LIS->InsertMachineInstrInMaps(*MI);
11201120
LiveInterval &LI = LIS->getInterval(AVLReg);
11211121
SlotIndex SI = LIS->getInstructionIndex(*MI).getRegSlot();
1122+
const VNInfo *CurVNI = Info.getAVLVNInfo();
11221123
// If the AVL value isn't live at MI, do a quick check to see if it's easily
11231124
// extendable. Otherwise, we need to copy it.
1124-
if (LI.getVNInfoBefore(SI) != Info.getAVLVNInfo()) {
1125+
if (LI.getVNInfoBefore(SI) != CurVNI) {
11251126
if (!LI.liveAt(SI) && LI.containsOneValue())
11261127
LIS->extendToIndices(LI, SI);
11271128
else {
11281129
Register AVLCopyReg =
11291130
MRI->createVirtualRegister(&RISCV::GPRNoX0RegClass);
1131+
MachineBasicBlock *MBB = LIS->getMBBFromIndex(CurVNI->def);
11301132
MachineBasicBlock::iterator II;
1131-
if (Info.getAVLVNInfo()->isPHIDef())
1132-
II = LIS->getMBBFromIndex(Info.getAVLVNInfo()->def)->getFirstNonPHI();
1133+
if (CurVNI->isPHIDef())
1134+
II = MBB->getFirstNonPHI();
11331135
else {
1134-
II = LIS->getInstructionFromIndex(Info.getAVLVNInfo()->def);
1136+
II = LIS->getInstructionFromIndex(CurVNI->def);
11351137
II = std::next(II);
11361138
}
11371139
assert(II.isValid());
1138-
auto AVLCopy =
1139-
BuildMI(*II->getParent(), II, DL, TII->get(RISCV::COPY), AVLCopyReg)
1140-
.addReg(AVLReg);
1140+
auto AVLCopy = BuildMI(*MBB, II, DL, TII->get(RISCV::COPY), AVLCopyReg)
1141+
.addReg(AVLReg);
11411142
LIS->InsertMachineInstrInMaps(*AVLCopy);
11421143
MI->getOperand(1).setReg(AVLCopyReg);
11431144
LIS->createAndComputeVirtRegInterval(AVLCopyReg);

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,10 @@
142142
ret void
143143
}
144144

145+
define void @avl_is_last_instr() {
146+
ret void
147+
}
148+
145149
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
146150

147151
declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
@@ -1099,3 +1103,66 @@ body: |
10991103
renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, %v, %v, -1, 5, 0
11001104
renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, killed %v, %outvl:gprnox0, 5, 0
11011105
PseudoRET implicit $v8m2
1106+
...
1107+
---
1108+
name: avl_is_last_instr
1109+
tracksRegLiveness: true
1110+
body: |
1111+
; CHECK-LABEL: name: avl_is_last_instr
1112+
; CHECK: bb.0:
1113+
; CHECK-NEXT: successors: %bb.1(0x80000000)
1114+
; CHECK-NEXT: liveins: $x10
1115+
; CHECK-NEXT: {{ $}}
1116+
; CHECK-NEXT: %base:gpr = COPY $x10
1117+
; CHECK-NEXT: %avl:gprnox0 = ADDI $x0, 256
1118+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY %avl
1119+
; CHECK-NEXT: {{ $}}
1120+
; CHECK-NEXT: bb.1:
1121+
; CHECK-NEXT: successors: %bb.2(0x80000000)
1122+
; CHECK-NEXT: {{ $}}
1123+
; CHECK-NEXT: dead %prevl:gprnox0 = PseudoVSETVLI %avl, 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype
1124+
; CHECK-NEXT: renamable $v8m8 = PseudoVMV_V_I_M8 undef renamable $v8m8, 0, $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
1125+
; CHECK-NEXT: {{ $}}
1126+
; CHECK-NEXT: bb.2:
1127+
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
1128+
; CHECK-NEXT: liveins: $v8m8
1129+
; CHECK-NEXT: {{ $}}
1130+
; CHECK-NEXT: %vl:gprnox0 = PseudoVSETVLI %avl, 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype
1131+
; CHECK-NEXT: renamable $v16m8 = PseudoVLE8_V_M8 undef renamable $v16m8, %base, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
1132+
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 131 /* e8, m8, tu, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
1133+
; CHECK-NEXT: renamable $v8m8 = PseudoVADD_VV_M8 killed renamable $v8m8, killed renamable $v16m8, renamable $v8m8, $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
1134+
; CHECK-NEXT: %base:gpr = ADD %base, %vl
1135+
; CHECK-NEXT: %avl:gprnox0 = SUB %avl, %vl
1136+
; CHECK-NEXT: BNE %avl, $x0, %bb.2
1137+
; CHECK-NEXT: {{ $}}
1138+
; CHECK-NEXT: bb.3:
1139+
; CHECK-NEXT: liveins: $v8m8
1140+
; CHECK-NEXT: {{ $}}
1141+
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype
1142+
; CHECK-NEXT: renamable $v16 = PseudoVMV_S_X undef renamable $v16, $x0, 1, 3 /* e8 */, implicit $vl, implicit $vtype
1143+
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype
1144+
; CHECK-NEXT: renamable $v16 = PseudoVREDSUM_VS_M8_E8 killed renamable $v16, killed renamable $v8m8, renamable $v16, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
1145+
; CHECK-NEXT: dead %res:gpr = PseudoVMV_X_S killed renamable $v16, 3 /* e8 */, implicit $vtype
1146+
bb.0:
1147+
liveins: $x10
1148+
%base:gpr = COPY $x10
1149+
%avl:gprnox0 = ADDI $x0, 256
1150+
1151+
bb.1:
1152+
%prevl:gprnox0 = PseudoVSETVLI %avl:gprnox0, 195, implicit-def dead $vl, implicit-def dead $vtype
1153+
renamable $v8m8 = PseudoVMV_V_I_M8 undef renamable $v8m8, 0, %prevl:gprnox0, 3, 0
1154+
1155+
bb.2:
1156+
liveins: $v8m8
1157+
%vl:gprnox0 = PseudoVSETVLI %avl:gprnox0, 195, implicit-def dead $vl, implicit-def dead $vtype
1158+
renamable $v16m8 = PseudoVLE8_V_M8 undef renamable $v16m8, %base:gpr, %vl:gprnox0, 3, 1
1159+
renamable $v8m8 = PseudoVADD_VV_M8 killed renamable $v8m8, killed renamable $v16m8, renamable $v8m8, %vl:gprnox0, 3, 0
1160+
%base:gpr = ADD %base:gpr, %vl:gprnox0
1161+
%avl:gprnox0 = SUB %avl:gprnox0, %vl:gprnox0
1162+
BNE %avl:gprnox0, $x0, %bb.2
1163+
1164+
bb.3:
1165+
liveins: $v8m8
1166+
renamable $v16 = PseudoVMV_S_X undef renamable $v16, $x0, 1, 3
1167+
renamable $v16 = PseudoVREDSUM_VS_M8_E8 killed renamable $v16, killed renamable $v8m8, renamable $v16, %prevl:gprnox0, 3, 1
1168+
%res:gpr = PseudoVMV_X_S killed renamable $v16, 3

0 commit comments

Comments
 (0)