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XinWang10XinWang10
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rewrite with ITy
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‎llvm/lib/Target/X86/X86InstrMisc.td

Lines changed: 30 additions & 78 deletions
Original file line numberDiff line numberDiff line change
@@ -1090,91 +1090,43 @@ def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
10901090
//===----------------------------------------------------------------------===//
10911091
// MOVBE Instructions
10921092
//
1093+
multiclass Movbe<bits<8> o, X86TypeInfo t, string suffix = ""> {
1094+
let SchedRW = [WriteALULd] in
1095+
def rm#suffix : ITy<o, MRMSrcMem, t, (outs t.RegClass:$dst),
1096+
(ins t.MemOperand:$src1), "movbe", unaryop_ndd_args,
1097+
[(set t.RegClass:$dst, (bswap (t.LoadNode addr:$src1)))]>;
1098+
let SchedRW = [WriteStore] in
1099+
def mr#suffix : ITy<!add(o, 1), MRMDestMem, t, (outs),
1100+
(ins t.MemOperand:$dst, t.RegClass:$src1),
1101+
"movbe", unaryop_ndd_args,
1102+
[(store (bswap t.RegClass:$src1), addr:$dst)]>;
1103+
}
1104+
10931105
let Predicates = [HasMOVBE, NoEGPR] in {
1094-
let SchedRW = [WriteALULd] in {
1095-
def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1096-
"movbe{w}\t{$src, $dst|$dst, $src}",
1097-
[(set GR16:$dst, (bswap (loadi16 addr:$src)))]>,
1098-
OpSize16, T8;
1099-
def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1100-
"movbe{l}\t{$src, $dst|$dst, $src}",
1101-
[(set GR32:$dst, (bswap (loadi32 addr:$src)))]>,
1102-
OpSize32, T8;
1103-
def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1104-
"movbe{q}\t{$src, $dst|$dst, $src}",
1105-
[(set GR64:$dst, (bswap (loadi64 addr:$src)))]>,
1106-
T8;
1107-
}
1108-
let SchedRW = [WriteStore] in {
1109-
def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1110-
"movbe{w}\t{$src, $dst|$dst, $src}",
1111-
[(store (bswap GR16:$src), addr:$dst)]>,
1112-
OpSize16, T8;
1113-
def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1114-
"movbe{l}\t{$src, $dst|$dst, $src}",
1115-
[(store (bswap GR32:$src), addr:$dst)]>,
1116-
OpSize32, T8;
1117-
def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1118-
"movbe{q}\t{$src, $dst|$dst, $src}",
1119-
[(store (bswap GR64:$src), addr:$dst)]>,
1120-
T8;
1121-
}
1106+
defm MOVBE16 : Movbe<0xF0, Xi16>, OpSize16, T8;
1107+
defm MOVBE32 : Movbe<0xF0, Xi32>, OpSize32, T8;
1108+
defm MOVBE64 : Movbe<0xF0, Xi64>, T8;
11221109
}
11231110

11241111
let Predicates = [HasMOVBE, HasEGPR, In64BitMode] in {
1125-
let SchedRW = [WriteALULd] in {
1126-
def MOVBE16rm_EVEX : I<0x60, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1127-
"movbe{w}\t{$src, $dst|$dst, $src}",
1128-
[(set GR16:$dst, (bswap (loadi16 addr:$src)))]>,
1129-
EVEX, NoCD8, T_MAP4, PD;
1130-
def MOVBE32rm_EVEX : I<0x60, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1131-
"movbe{l}\t{$src, $dst|$dst, $src}",
1132-
[(set GR32:$dst, (bswap (loadi32 addr:$src)))]>,
1133-
EVEX, NoCD8, T_MAP4;
1134-
def MOVBE64rm_EVEX : RI<0x60, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1135-
"movbe{q}\t{$src, $dst|$dst, $src}",
1136-
[(set GR64:$dst, (bswap (loadi64 addr:$src)))]>,
1137-
EVEX, NoCD8, T_MAP4;
1138-
}
1139-
let SchedRW = [WriteStore] in {
1140-
def MOVBE16mr_EVEX : I<0x61, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1141-
"movbe{w}\t{$src, $dst|$dst, $src}",
1142-
[(store (bswap GR16:$src), addr:$dst)]>,
1143-
EVEX, NoCD8, T_MAP4, PD;
1144-
def MOVBE32mr_EVEX : I<0x61, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1145-
"movbe{l}\t{$src, $dst|$dst, $src}",
1146-
[(store (bswap GR32:$src), addr:$dst)]>,
1147-
EVEX, NoCD8, T_MAP4;
1148-
def MOVBE64mr_EVEX : RI<0x61, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1149-
"movbe{q}\t{$src, $dst|$dst, $src}",
1150-
[(store (bswap GR64:$src), addr:$dst)]>,
1151-
EVEX, NoCD8, T_MAP4;
1152-
}
1112+
defm MOVBE16 : Movbe<0x60, Xi16, "_EVEX">, EVEX, T_MAP4, PD;
1113+
defm MOVBE32 : Movbe<0x60, Xi32, "_EVEX">, EVEX, T_MAP4;
1114+
defm MOVBE64 : Movbe<0x60, Xi64, "_EVEX">, EVEX, T_MAP4;
11531115
}
11541116

1117+
multiclass Movberr<X86TypeInfo t> {
1118+
def rr_EVEX : ITy<0x61, MRMDestReg, t, (outs t.RegClass:$dst),
1119+
(ins t.RegClass:$src1), "movbe", unaryop_ndd_args,
1120+
[(set t.RegClass:$dst, (bswap t.RegClass:$src1))]>,
1121+
EVEX, T_MAP4;
1122+
def rr_EVEX_REV : ITy<0x60, MRMSrcReg, t, (outs t.RegClass:$dst),
1123+
(ins t.RegClass:$src1), "movbe", unaryop_ndd_args, []>,
1124+
EVEX, T_MAP4, DisassembleOnly;
1125+
}
11551126
let SchedRW = [WriteALU], Predicates = [HasMOVBE, HasNDD, In64BitMode] in {
1156-
def MOVBE16rr_EVEX : I<0x61, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1157-
"movbe{w}\t{$src, $dst|$dst, $src}",
1158-
[(set GR16:$dst, (bswap GR16:$src))]>,
1159-
EVEX, NoCD8, T_MAP4, PD;
1160-
def MOVBE32rr_EVEX : I<0x61, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1161-
"movbe{l}\t{$src, $dst|$dst, $src}",
1162-
[(set GR32:$dst, (bswap GR32:$src))]>,
1163-
EVEX, NoCD8, T_MAP4;
1164-
def MOVBE64rr_EVEX : RI<0x61, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1165-
"movbe{q}\t{$src, $dst|$dst, $src}",
1166-
[(set GR64:$dst, (bswap GR64:$src))]>,
1167-
EVEX, NoCD8, T_MAP4;
1168-
1169-
def MOVBE16rr_EVEX_REV : I<0x60, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1170-
"movbe{w}\t{$src, $dst|$dst, $src}", []>,
1171-
EVEX, NoCD8, T_MAP4, PD, DisassembleOnly;
1172-
def MOVBE32rr_EVEX_REV : I<0x60, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1173-
"movbe{l}\t{$src, $dst|$dst, $src}", []>,
1174-
EVEX, NoCD8, T_MAP4, DisassembleOnly;
1175-
def MOVBE64rr_EVEX_REV : RI<0x60, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1176-
"movbe{q}\t{$src, $dst|$dst, $src}", []>,
1177-
EVEX, NoCD8, T_MAP4, DisassembleOnly;
1127+
defm MOVBE16 : Movberr<Xi16>, PD;
1128+
defm MOVBE32 : Movberr<Xi32>;
1129+
defm MOVBE64 : Movberr<Xi64>;
11781130
}
11791131

11801132
//===----------------------------------------------------------------------===//

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