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[VPlan] Move up VPRecipeWithIRFlags definition. (NFC)
This allows using VPRecipeWithIRFlags for VPInstruction and reduces the diff for D157144 & D157194.
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  • llvm/lib/Transforms/Vectorize

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llvm/lib/Transforms/Vectorize/VPlan.h

Lines changed: 135 additions & 135 deletions
Original file line numberDiff line numberDiff line change
@@ -811,141 +811,6 @@ class VPRecipeBase : public ilist_node_with_parent<VPRecipeBase, VPBasicBlock>,
811811
return R->getVPDefID() == VPDefID; \
812812
}
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/// This is a concrete Recipe that models a single VPlan-level instruction.
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/// While as any Recipe it may generate a sequence of IR instructions when
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/// executed, these instructions would always form a single-def expression as
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/// the VPInstruction is also a single def-use vertex.
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class VPInstruction : public VPRecipeBase, public VPValue {
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friend class VPlanSlp;
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821-
public:
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/// VPlan opcodes, extending LLVM IR with idiomatics instructions.
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enum {
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FirstOrderRecurrenceSplice =
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Instruction::OtherOpsEnd + 1, // Combines the incoming and previous
826-
// values of a first-order recurrence.
827-
Not,
828-
ICmpULE,
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SLPLoad,
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SLPStore,
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ActiveLaneMask,
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CalculateTripCountMinusVF,
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CanonicalIVIncrement,
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CanonicalIVIncrementNUW,
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// The next two are similar to the above, but instead increment the
836-
// canonical IV separately for each unrolled part.
837-
CanonicalIVIncrementForPart,
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CanonicalIVIncrementForPartNUW,
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BranchOnCount,
840-
BranchOnCond
841-
};
842-
843-
private:
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typedef unsigned char OpcodeTy;
845-
OpcodeTy Opcode;
846-
FastMathFlags FMF;
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DebugLoc DL;
848-
849-
/// An optional name that can be used for the generated IR instruction.
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const std::string Name;
851-
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/// Utility method serving execute(): generates a single instance of the
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/// modeled instruction. \returns the generated value for \p Part.
854-
/// In some cases an existing value is returned rather than a generated
855-
/// one.
856-
Value *generateInstruction(VPTransformState &State, unsigned Part);
857-
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protected:
859-
void setUnderlyingInstr(Instruction *I) { setUnderlyingValue(I); }
860-
861-
public:
862-
VPInstruction(unsigned Opcode, ArrayRef<VPValue *> Operands, DebugLoc DL,
863-
const Twine &Name = "")
864-
: VPRecipeBase(VPDef::VPInstructionSC, Operands), VPValue(this),
865-
Opcode(Opcode), DL(DL), Name(Name.str()) {}
866-
867-
VPInstruction(unsigned Opcode, std::initializer_list<VPValue *> Operands,
868-
DebugLoc DL = {}, const Twine &Name = "")
869-
: VPInstruction(Opcode, ArrayRef<VPValue *>(Operands), DL, Name) {}
870-
871-
VP_CLASSOF_IMPL(VPDef::VPInstructionSC)
872-
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VPInstruction *clone() const {
874-
SmallVector<VPValue *, 2> Operands(operands());
875-
return new VPInstruction(Opcode, Operands, DL, Name);
876-
}
877-
878-
unsigned getOpcode() const { return Opcode; }
879-
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/// Generate the instruction.
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/// TODO: We currently execute only per-part unless a specific instance is
882-
/// provided.
883-
void execute(VPTransformState &State) override;
884-
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
886-
/// Print the VPInstruction to \p O.
887-
void print(raw_ostream &O, const Twine &Indent,
888-
VPSlotTracker &SlotTracker) const override;
889-
890-
/// Print the VPInstruction to dbgs() (for debugging).
891-
LLVM_DUMP_METHOD void dump() const;
892-
#endif
893-
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/// Return true if this instruction may modify memory.
895-
bool mayWriteToMemory() const {
896-
// TODO: we can use attributes of the called function to rule out memory
897-
// modifications.
898-
return Opcode == Instruction::Store || Opcode == Instruction::Call ||
899-
Opcode == Instruction::Invoke || Opcode == SLPStore;
900-
}
901-
902-
bool hasResult() const {
903-
// CallInst may or may not have a result, depending on the called function.
904-
// Conservatively return calls have results for now.
905-
switch (getOpcode()) {
906-
case Instruction::Ret:
907-
case Instruction::Br:
908-
case Instruction::Store:
909-
case Instruction::Switch:
910-
case Instruction::IndirectBr:
911-
case Instruction::Resume:
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case Instruction::CatchRet:
913-
case Instruction::Unreachable:
914-
case Instruction::Fence:
915-
case Instruction::AtomicRMW:
916-
case VPInstruction::BranchOnCond:
917-
case VPInstruction::BranchOnCount:
918-
return false;
919-
default:
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return true;
921-
}
922-
}
923-
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/// Set the fast-math flags.
925-
void setFastMathFlags(FastMathFlags FMFNew);
926-
927-
/// Returns true if the recipe only uses the first lane of operand \p Op.
928-
bool onlyFirstLaneUsed(const VPValue *Op) const override {
929-
assert(is_contained(operands(), Op) &&
930-
"Op must be an operand of the recipe");
931-
if (getOperand(0) != Op)
932-
return false;
933-
switch (getOpcode()) {
934-
default:
935-
return false;
936-
case VPInstruction::ActiveLaneMask:
937-
case VPInstruction::CalculateTripCountMinusVF:
938-
case VPInstruction::CanonicalIVIncrement:
939-
case VPInstruction::CanonicalIVIncrementNUW:
940-
case VPInstruction::CanonicalIVIncrementForPart:
941-
case VPInstruction::CanonicalIVIncrementForPartNUW:
942-
case VPInstruction::BranchOnCount:
943-
return true;
944-
};
945-
llvm_unreachable("switch should return");
946-
}
947-
};
948-
949814
/// Class to record LLVM IR flag for a recipe along with it.
950815
class VPRecipeWithIRFlags : public VPRecipeBase {
951816
enum class OperationType : unsigned char {
@@ -1100,6 +965,141 @@ class VPRecipeWithIRFlags : public VPRecipeBase {
1100965
#endif
1101966
};
1102967

968+
/// This is a concrete Recipe that models a single VPlan-level instruction.
969+
/// While as any Recipe it may generate a sequence of IR instructions when
970+
/// executed, these instructions would always form a single-def expression as
971+
/// the VPInstruction is also a single def-use vertex.
972+
class VPInstruction : public VPRecipeBase, public VPValue {
973+
friend class VPlanSlp;
974+
975+
public:
976+
/// VPlan opcodes, extending LLVM IR with idiomatics instructions.
977+
enum {
978+
FirstOrderRecurrenceSplice =
979+
Instruction::OtherOpsEnd + 1, // Combines the incoming and previous
980+
// values of a first-order recurrence.
981+
Not,
982+
ICmpULE,
983+
SLPLoad,
984+
SLPStore,
985+
ActiveLaneMask,
986+
CalculateTripCountMinusVF,
987+
CanonicalIVIncrement,
988+
CanonicalIVIncrementNUW,
989+
// The next two are similar to the above, but instead increment the
990+
// canonical IV separately for each unrolled part.
991+
CanonicalIVIncrementForPart,
992+
CanonicalIVIncrementForPartNUW,
993+
BranchOnCount,
994+
BranchOnCond
995+
};
996+
997+
private:
998+
typedef unsigned char OpcodeTy;
999+
OpcodeTy Opcode;
1000+
FastMathFlags FMF;
1001+
DebugLoc DL;
1002+
1003+
/// An optional name that can be used for the generated IR instruction.
1004+
const std::string Name;
1005+
1006+
/// Utility method serving execute(): generates a single instance of the
1007+
/// modeled instruction. \returns the generated value for \p Part.
1008+
/// In some cases an existing value is returned rather than a generated
1009+
/// one.
1010+
Value *generateInstruction(VPTransformState &State, unsigned Part);
1011+
1012+
protected:
1013+
void setUnderlyingInstr(Instruction *I) { setUnderlyingValue(I); }
1014+
1015+
public:
1016+
VPInstruction(unsigned Opcode, ArrayRef<VPValue *> Operands, DebugLoc DL,
1017+
const Twine &Name = "")
1018+
: VPRecipeBase(VPDef::VPInstructionSC, Operands), VPValue(this),
1019+
Opcode(Opcode), DL(DL), Name(Name.str()) {}
1020+
1021+
VPInstruction(unsigned Opcode, std::initializer_list<VPValue *> Operands,
1022+
DebugLoc DL = {}, const Twine &Name = "")
1023+
: VPInstruction(Opcode, ArrayRef<VPValue *>(Operands), DL, Name) {}
1024+
1025+
VP_CLASSOF_IMPL(VPDef::VPInstructionSC)
1026+
1027+
VPInstruction *clone() const {
1028+
SmallVector<VPValue *, 2> Operands(operands());
1029+
return new VPInstruction(Opcode, Operands, DL, Name);
1030+
}
1031+
1032+
unsigned getOpcode() const { return Opcode; }
1033+
1034+
/// Generate the instruction.
1035+
/// TODO: We currently execute only per-part unless a specific instance is
1036+
/// provided.
1037+
void execute(VPTransformState &State) override;
1038+
1039+
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1040+
/// Print the VPInstruction to \p O.
1041+
void print(raw_ostream &O, const Twine &Indent,
1042+
VPSlotTracker &SlotTracker) const override;
1043+
1044+
/// Print the VPInstruction to dbgs() (for debugging).
1045+
LLVM_DUMP_METHOD void dump() const;
1046+
#endif
1047+
1048+
/// Return true if this instruction may modify memory.
1049+
bool mayWriteToMemory() const {
1050+
// TODO: we can use attributes of the called function to rule out memory
1051+
// modifications.
1052+
return Opcode == Instruction::Store || Opcode == Instruction::Call ||
1053+
Opcode == Instruction::Invoke || Opcode == SLPStore;
1054+
}
1055+
1056+
bool hasResult() const {
1057+
// CallInst may or may not have a result, depending on the called function.
1058+
// Conservatively return calls have results for now.
1059+
switch (getOpcode()) {
1060+
case Instruction::Ret:
1061+
case Instruction::Br:
1062+
case Instruction::Store:
1063+
case Instruction::Switch:
1064+
case Instruction::IndirectBr:
1065+
case Instruction::Resume:
1066+
case Instruction::CatchRet:
1067+
case Instruction::Unreachable:
1068+
case Instruction::Fence:
1069+
case Instruction::AtomicRMW:
1070+
case VPInstruction::BranchOnCond:
1071+
case VPInstruction::BranchOnCount:
1072+
return false;
1073+
default:
1074+
return true;
1075+
}
1076+
}
1077+
1078+
/// Set the fast-math flags.
1079+
void setFastMathFlags(FastMathFlags FMFNew);
1080+
1081+
/// Returns true if the recipe only uses the first lane of operand \p Op.
1082+
bool onlyFirstLaneUsed(const VPValue *Op) const override {
1083+
assert(is_contained(operands(), Op) &&
1084+
"Op must be an operand of the recipe");
1085+
if (getOperand(0) != Op)
1086+
return false;
1087+
switch (getOpcode()) {
1088+
default:
1089+
return false;
1090+
case VPInstruction::ActiveLaneMask:
1091+
case VPInstruction::CalculateTripCountMinusVF:
1092+
case VPInstruction::CanonicalIVIncrement:
1093+
case VPInstruction::CanonicalIVIncrementNUW:
1094+
case VPInstruction::CanonicalIVIncrementForPart:
1095+
case VPInstruction::CanonicalIVIncrementForPartNUW:
1096+
case VPInstruction::BranchOnCount:
1097+
return true;
1098+
};
1099+
llvm_unreachable("switch should return");
1100+
}
1101+
};
1102+
11031103
/// VPWidenRecipe is a recipe for producing a copy of vector type its
11041104
/// ingredient. This recipe covers most of the traditional vectorization cases
11051105
/// where each ingredient transforms into a vectorized version of itself.

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