Skip to content

Commit 7b45c54

Browse files
authored
[MC][RISCV] Check hasEmitNops before call shouldInsertExtraNopBytesForCodeAlign (#77236)
The shouldInsertExtraNopBytesForCodeAlign() need STI to check whether relax is enabled or not. It is initialized when call setEmitNops. The setEmitNops may not be called in a section which has instructions but is not executable. In this case uninitialized STI will cause problems. Thus, check hasEmitNops before call it. Fixes: #76552 (comment)
1 parent b57159c commit 7b45c54

File tree

2 files changed

+26
-1
lines changed

2 files changed

+26
-1
lines changed

llvm/lib/MC/MCExpr.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -708,7 +708,7 @@ static void AttemptToFoldSymbolOffsetDifference(
708708
if (DF) {
709709
Displacement += DF->getContents().size();
710710
} else if (auto *AF = dyn_cast<MCAlignFragment>(FI);
711-
AF && Layout &&
711+
AF && Layout && AF->hasEmitNops() &&
712712
!Asm->getBackend().shouldInsertExtraNopBytesForCodeAlign(
713713
*AF, Count)) {
714714
Displacement += Asm->computeFragmentSize(*Layout, *AF);
Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
## A label difference separated by an alignment directive, when the
2+
## referenced symbols are in a non-executable section with instructions,
3+
## should generate ADD/SUB relocations.
4+
## https://github.com/llvm/llvm-project/pull/76552
5+
6+
# RUN: llvm-mc --filetype=obj --triple=riscv64 --mattr=+relax %s \
7+
# RUN: | llvm-readobj -r - | FileCheck --check-prefixes=CHECK,RELAX %s
8+
# RUN: llvm-mc --filetype=obj --triple=riscv64 --mattr=-relax %s \
9+
# RUN: | llvm-readobj -r - | FileCheck %s
10+
11+
.section ".dummy", "a"
12+
.L1:
13+
call func
14+
.p2align 3
15+
.L2:
16+
.dword .L2 - .L1
17+
18+
# CHECK: Relocations [
19+
# CHECK-NEXT: Section ({{.*}}) .rela.dummy {
20+
# CHECK-NEXT: 0x0 R_RISCV_CALL_PLT func 0x0
21+
# RELAX-NEXT: 0x0 R_RISCV_RELAX - 0x0
22+
# CHECK-NEXT: 0x8 R_RISCV_ADD64 .L2 0x0
23+
# CHECK-NEXT: 0x8 R_RISCV_SUB64 .L1 0x0
24+
# CHECK-NEXT: }
25+
# CHECK-NEXT: ]

0 commit comments

Comments
 (0)