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[mips] Implement Octeon+ saa and saad instructions
`saa` and `saad` are 32-bit and 64-bit store atomic add instructions. memory[base] = memory[base] + rt These instructions are available for "Octeon+" CPU. The patch adds support for both instructions to MIPS assembler and diassembler and introduces new CPU type - "octeon+". Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP` ISA extension flag support. Differential Revision: https://reviews.llvm.org/D69849
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18 files changed

+410
-16
lines changed

18 files changed

+410
-16
lines changed

‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Lines changed: 48 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -126,7 +126,8 @@ const FeatureBitset MipsAssemblerOptions::AllArchRelatedMask = {
126126
Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
127127
Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
128128
Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
129-
Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008
129+
Mips::FeatureCnMipsP, Mips::FeatureFP64Bit, Mips::FeatureGP64Bit,
130+
Mips::FeatureNaN2008
130131
};
131132

132133
namespace {
@@ -330,6 +331,9 @@ class MipsAsmParser : public MCTargetAsmParser {
330331
bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
331332
const MCSubtargetInfo *STI);
332333

334+
bool expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
335+
const MCSubtargetInfo *STI);
336+
333337
bool reportParseError(Twine ErrorMsg);
334338
bool reportParseError(SMLoc Loc, Twine ErrorMsg);
335339

@@ -654,6 +658,10 @@ class MipsAsmParser : public MCTargetAsmParser {
654658
return (getSTI().getFeatureBits()[Mips::FeatureCnMips]);
655659
}
656660

661+
bool hasCnMipsP() const {
662+
return (getSTI().getFeatureBits()[Mips::FeatureCnMipsP]);
663+
}
664+
657665
bool inPicMode() {
658666
return IsPicEnabled;
659667
}
@@ -2545,6 +2553,9 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
25452553
case Mips::MFTHC1: case Mips::MTTHC1:
25462554
case Mips::CFTC1: case Mips::CTTC1:
25472555
return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2556+
case Mips::SaaAddr:
2557+
case Mips::SaadAddr:
2558+
return expandSaaAddr(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
25482559
}
25492560
}
25502561

@@ -3041,7 +3052,7 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
30413052
TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI);
30423053

30433054
return false;
3044-
} else if (canUseATReg() && !RdRegIsRsReg) {
3055+
} else if (canUseATReg() && !RdRegIsRsReg && DstReg != getATReg(IDLoc)) {
30453056
unsigned ATReg = getATReg(IDLoc);
30463057

30473058
// If the $rs is different from $rd or if $rs isn't specified and we
@@ -3068,7 +3079,8 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
30683079
TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);
30693080

30703081
return false;
3071-
} else if (!canUseATReg() && !RdRegIsRsReg) {
3082+
} else if ((!canUseATReg() && !RdRegIsRsReg) ||
3083+
(canUseATReg() && DstReg == getATReg(IDLoc))) {
30723084
// Otherwise, synthesize the address in the destination register
30733085
// serially:
30743086
// (d)la $rd, sym/sym($rs) => lui $rd, %highest(sym)
@@ -5412,6 +5424,39 @@ bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
54125424
return false;
54135425
}
54145426

5427+
bool MipsAsmParser::expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5428+
const MCSubtargetInfo *STI) {
5429+
assert(Inst.getNumOperands() == 3 && "expected three operands");
5430+
assert(Inst.getOperand(0).isReg() && "expected register operand kind");
5431+
assert(Inst.getOperand(1).isReg() && "expected register operand kind");
5432+
5433+
warnIfNoMacro(IDLoc);
5434+
5435+
MipsTargetStreamer &TOut = getTargetStreamer();
5436+
unsigned Opcode = Inst.getOpcode() == Mips::SaaAddr ? Mips::SAA : Mips::SAAD;
5437+
unsigned RtReg = Inst.getOperand(0).getReg();
5438+
unsigned BaseReg = Inst.getOperand(1).getReg();
5439+
const MCOperand &BaseOp = Inst.getOperand(2);
5440+
5441+
if (BaseOp.isImm()) {
5442+
int64_t ImmValue = BaseOp.getImm();
5443+
if (ImmValue == 0) {
5444+
TOut.emitRR(Opcode, RtReg, BaseReg, IDLoc, STI);
5445+
return false;
5446+
}
5447+
}
5448+
5449+
unsigned ATReg = getATReg(IDLoc);
5450+
if (!ATReg)
5451+
return true;
5452+
5453+
if (expandLoadAddress(ATReg, BaseReg, BaseOp, !isGP64bit(), IDLoc, Out, STI))
5454+
return true;
5455+
5456+
TOut.emitRR(Opcode, RtReg, ATReg, IDLoc, STI);
5457+
return false;
5458+
}
5459+
54155460
unsigned
54165461
MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
54175462
const OperandVector &Operands) {

‎llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,8 @@ class MipsDisassembler : public MCDisassembler {
6363

6464
bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
6565

66+
bool hasCnMipsP() const { return STI.getFeatureBits()[Mips::FeatureCnMipsP]; }
67+
6668
bool hasCOP3() const {
6769
// Only present in MIPS-I and MIPS-II
6870
return !hasMips32() && !hasMips3();
@@ -1357,6 +1359,14 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
13571359
return Result;
13581360
}
13591361

1362+
if (hasCnMipsP()) {
1363+
LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n");
1364+
Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn,
1365+
Address, this, STI);
1366+
if (Result != MCDisassembler::Fail)
1367+
return Result;
1368+
}
1369+
13601370
if (isGP64()) {
13611371
LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
13621372
Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,

‎llvm/lib/Target/Mips/Mips.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -196,6 +196,10 @@ def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
196196
"true", "Octeon cnMIPS Support",
197197
[FeatureMips64r2]>;
198198

199+
def FeatureCnMipsP : SubtargetFeature<"cnmipsp", "HasCnMipsP",
200+
"true", "Octeon+ cnMIPS Support",
201+
[FeatureCnMips]>;
202+
199203
def FeatureUseTCCInDIV : SubtargetFeature<
200204
"use-tcc-in-div",
201205
"UseTCCInDIV", "false",
@@ -245,6 +249,7 @@ def : Proc<"mips64r3", [FeatureMips64r3]>;
245249
def : Proc<"mips64r5", [FeatureMips64r5]>;
246250
def : Proc<"mips64r6", [FeatureMips64r6]>;
247251
def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
252+
def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
248253
def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
249254

250255
def MipsAsmParser : AsmParser {

‎llvm/lib/Target/Mips/Mips64InstrInfo.td

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -586,6 +586,24 @@ def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd, II_DMTC2>, MFC2OP_FM<0x12, 5>,
586586
ASE_CNMIPS;
587587
}
588588

589+
// Cavium Octeon+ cnMIPS instructions
590+
let DecoderNamespace = "CnMipsP",
591+
// FIXME: The lack of HasStdEnc is probably a bug
592+
EncodingPredicates = []<Predicate> in {
593+
594+
class Saa<string opstr>:
595+
InstSE<(outs), (ins GPR64Opnd:$rt, GPR64Opnd:$rs),
596+
!strconcat(opstr, "\t$rt, (${rs})"), [], NoItinerary, FrmR, opstr>;
597+
598+
def SAA : Saa<"saa">, SAA_FM<0x18>, ASE_CNMIPSP;
599+
def SAAD : Saa<"saad">, SAA_FM<0x19>, ASE_CNMIPSP;
600+
601+
def SaaAddr : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rt, mem:$addr),
602+
"saa\t$rt, $addr">, ASE_CNMIPSP;
603+
def SaadAddr : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rt, mem:$addr),
604+
"saad\t$rt, $addr">, ASE_CNMIPSP;
605+
}
606+
589607
}
590608

591609
/// Move between CPU and coprocessor registers

‎llvm/lib/Target/Mips/MipsInstrFormats.td

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -626,6 +626,19 @@ class SEQI_FM<bits<6> funct> : StdArch {
626626
let Inst{5-0} = funct;
627627
}
628628

629+
class SAA_FM<bits<6> funct> : StdArch {
630+
bits<5> rt;
631+
bits<5> rs;
632+
633+
bits<32> Inst;
634+
635+
let Inst{31-26} = 0x1c;
636+
let Inst{25-21} = rs;
637+
let Inst{20-16} = rt;
638+
let Inst{15-6} = 0;
639+
let Inst{5-0} = funct;
640+
}
641+
629642
//===----------------------------------------------------------------------===//
630643
// System calls format <op|code_|funct>
631644
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/Mips/MipsInstrInfo.td

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -211,6 +211,10 @@ def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
211211
AssemblerPredicate<"FeatureCnMips">;
212212
def NotCnMips : Predicate<"!Subtarget->hasCnMips()">,
213213
AssemblerPredicate<"!FeatureCnMips">;
214+
def HasCnMipsP : Predicate<"Subtarget->hasCnMipsP()">,
215+
AssemblerPredicate<"FeatureCnMipsP">;
216+
def NotCnMipsP : Predicate<"!Subtarget->hasCnMipsP()">,
217+
AssemblerPredicate<"!FeatureCnMipsP">;
214218
def IsSym32 : Predicate<"Subtarget->hasSym32()">,
215219
AssemblerPredicate<"FeatureSym32">;
216220
def IsSym64 : Predicate<"!Subtarget->hasSym32()">,
@@ -439,6 +443,14 @@ class NOT_ASE_CNMIPS {
439443
list<Predicate> ASEPredicate = [NotCnMips];
440444
}
441445

446+
class ASE_CNMIPSP {
447+
list<Predicate> ASEPredicate = [HasCnMipsP];
448+
}
449+
450+
class NOT_ASE_CNMIPSP {
451+
list<Predicate> ASEPredicate = [NotCnMipsP];
452+
}
453+
442454
class ASE_MIPS64_CNMIPS {
443455
list<Predicate> ASEPredicate = [HasMips64, HasCnMips];
444456
}

‎llvm/lib/Target/Mips/MipsScheduleGeneric.td

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -720,11 +720,16 @@ def : InstRW<[GenericWriteALU], (instrs BADDu, BBIT0, BBIT032, BBIT1, BBIT132,
720720
CINS, CINS32, CINS64_32, CINS_i32,
721721
DMFC2_OCTEON, DMTC2_OCTEON, DPOP, EXTS,
722722
EXTS32, MTM0, MTM1, MTM2, MTP0, MTP1, MTP2,
723-
POP, SEQ, SEQi, SNE, SNEi, V3MULU, VMM0,
724-
VMULU)>;
723+
POP, SEQ, SEQi, SNE, SNEi,
724+
V3MULU, VMM0, VMULU)>;
725725

726726
def : InstRW<[GenericWriteMDUtoGPR], (instrs DMUL)>;
727727

728+
// Cavium Networks MIPS (cnMIPSP) - Octeon+, HasCnMipsP
729+
// =================================================
730+
731+
def : InstRW<[GenericWriteALU], (instrs SAA, SAAD)>;
732+
728733
// FPU Pipelines
729734
// =============
730735

‎llvm/lib/Target/Mips/MipsScheduleP5600.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,8 @@ def MipsP5600Model : SchedMachineModel {
1818
list<Predicate> UnsupportedFeatures = [HasMips3, HasMips32r6, HasMips64,
1919
HasMips64r2, HasMips64r5, HasMips64r6,
2020
IsGP64bit, IsPTR64bit,
21-
InMicroMips, InMips16Mode, HasCnMips,
21+
InMicroMips, InMips16Mode,
22+
HasCnMips, HasCnMipsP,
2223
HasDSP, HasDSPR2, HasMT, HasCRC];
2324
}
2425

‎llvm/lib/Target/Mips/MipsSubtarget.cpp

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -74,16 +74,17 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
7474
IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
7575
NoABICalls(false), Abs2008(false), IsFP64bit(false), UseOddSPReg(true),
7676
IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
77-
HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
78-
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
79-
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
80-
HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
81-
Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
82-
HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
83-
HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false),
84-
StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
85-
TSInfo(), InstrInfo(MipsInstrInfo::create(
86-
initializeSubtargetDependencies(CPU, FS, TM))),
77+
HasCnMipsP(false), HasMips3_32(false), HasMips3_32r2(false),
78+
HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
79+
InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
80+
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), HasDSPR3(false),
81+
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
82+
UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false),
83+
HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false),
84+
UseIndirectJumpsHazard(false), StackAlignOverride(StackAlignOverride),
85+
TM(TM), TargetTriple(TT), TSInfo(),
86+
InstrInfo(
87+
MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
8788
FrameLowering(MipsFrameLowering::create(*this)),
8889
TLInfo(MipsTargetLowering::create(TM, *this)) {
8990

‎llvm/lib/Target/Mips/MipsSubtarget.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -111,6 +111,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
111111
// CPU supports cnMIPS (Cavium Networks Octeon CPU).
112112
bool HasCnMips;
113113

114+
// CPU supports cnMIPSP (Cavium Networks Octeon+ CPU).
115+
bool HasCnMipsP;
116+
114117
// isLinux - Target system is Linux. Is false we consider ELFOS for now.
115118
bool IsLinux;
116119

@@ -270,6 +273,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
270273
bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
271274

272275
bool hasCnMips() const { return HasCnMips; }
276+
bool hasCnMipsP() const { return HasCnMipsP; }
273277

274278
bool isLittle() const { return IsLittle; }
275279
bool isABICalls() const { return !NoABICalls; }

‎llvm/test/MC/Disassembler/Mips/octeonp/valid-el.txt

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
# RUN: llvm-mc %s -disassemble -triple=mips64el-unknown-linux -mcpu=octeon+ \
2+
# RUN: | FileCheck %s
3+
4+
0x00 0x00 0x76 0xca # CHECK: bbit0 $19, 22, 4
5+
0x28 0x48 0xc7 0x70 # CHECK: baddu $9, $6, $7
6+
0x00 0x00 0x0a 0xd9 # CHECK: bbit032 $8, 10, 4
7+
0x00 0x00 0x7f 0xe8 # CHECK: bbit1 $3, 31, 4
8+
0x00 0x00 0x0a 0xfb # CHECK: bbit132 $24, 10, 4
9+
0x72 0xec 0x29 0x71 # CHECK: cins $9, $9, 17, 29
10+
0xb3 0x44 0x4f 0x70 # CHECK: cins32 $15, $2, 18, 8
11+
0x03 0x48 0xc7 0x70 # CHECK: dmul $9, $6, $7
12+
0x40 0x00 0x22 0x48 # CHECK: dmfc2 $2, 64
13+
0x47 0x40 0xa2 0x48 # CHECK: dmtc2 $2, 16455
14+
0x2d 0x48 0xc0 0x70 # CHECK: dpop $9, $6
15+
0x7a 0x34 0xef 0x71 # CHECK: exts $15, $15, 17, 6
16+
0xbb 0x42 0xa4 0x71 # CHECK: exts32 $4, $13, 10, 8
17+
0x08 0x00 0xe0 0x71 # CHECK: mtm0 $15
18+
0x0c 0x00 0x00 0x72 # CHECK: mtm1 $16
19+
0x0d 0x00 0x20 0x72 # CHECK: mtm2 $17
20+
0x09 0x00 0x40 0x72 # CHECK: mtp0 $18
21+
0x0a 0x00 0x60 0x72 # CHECK: mtp1 $19
22+
0x0b 0x00 0x80 0x72 # CHECK: mtp2 $20
23+
0x2c 0x48 0xc0 0x70 # CHECK: pop $9, $6
24+
0x18 0x00 0xa2 0x70 # CHECK: saa $2, ($5)
25+
0x19 0x00 0xa2 0x70 # CHECK: saad $2, ($5)
26+
0x2a 0xc8 0xf8 0x72 # CHECK: seq $25, $23, $24
27+
0xae 0x09 0x10 0x72 # CHECK: seqi $16, $16, 38
28+
0x2b 0xb8 0xf4 0x72 # CHECK: sne $23, $23, $20
29+
0xef 0xb1 0x04 0x72 # CHECK: snei $4, $16, -313
30+
0x8f 0x01 0x00 0x00 # CHECK: sync 6
31+
0x11 0xa8 0x55 0x71 # CHECK: v3mulu $21, $10, $21
32+
0x10 0x18 0x70 0x72 # CHECK: vmm0 $3, $19, $16
33+
0x0f 0xd8 0x66 0x73 # CHECK: vmulu $27, $27, $6

‎llvm/test/MC/Disassembler/Mips/octeonp/valid.txt

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
# RUN: llvm-mc %s -disassemble -triple=mips64-unknown-linux -mcpu=octeon+ \
2+
# RUN: | FileCheck %s
3+
4+
0xca 0x76 0x00 0x00 # CHECK: bbit0 $19, 22, 4
5+
0x70 0xc7 0x48 0x28 # CHECK: baddu $9, $6, $7
6+
0xd9 0x0a 0x00 0x00 # CHECK: bbit032 $8, 10, 4
7+
0xe8 0x7f 0x00 0x00 # CHECK: bbit1 $3, 31, 4
8+
0xfb 0x0a 0x00 0x00 # CHECK: bbit132 $24, 10, 4
9+
0x71 0x29 0xec 0x72 # CHECK: cins $9, $9, 17, 29
10+
0x70 0x4f 0x44 0xb3 # CHECK: cins32 $15, $2, 18, 8
11+
0x70 0xc7 0x48 0x03 # CHECK: dmul $9, $6, $7
12+
0x48 0x22 0x00 0x40 # CHECK: dmfc2 $2, 64
13+
0x48 0xa2 0x40 0x47 # CHECK: dmtc2 $2, 16455
14+
0x70 0xc0 0x48 0x2d # CHECK: dpop $9, $6
15+
0x71 0xef 0x34 0x7a # CHECK: exts $15, $15, 17, 6
16+
0x71 0xa4 0x42 0xbb # CHECK: exts32 $4, $13, 10, 8
17+
0x71 0xe0 0x00 0x08 # CHECK: mtm0 $15
18+
0x72 0x00 0x00 0x0c # CHECK: mtm1 $16
19+
0x72 0x20 0x00 0x0d # CHECK: mtm2 $17
20+
0x72 0x40 0x00 0x09 # CHECK: mtp0 $18
21+
0x72 0x60 0x00 0x0a # CHECK: mtp1 $19
22+
0x72 0x80 0x00 0x0b # CHECK: mtp2 $20
23+
0x70 0xc0 0x48 0x2c # CHECK: pop $9, $6
24+
0x70 0xa2 0x00 0x18 # CHECK: saa $2, ($5)
25+
0x70 0xa2 0x00 0x19 # CHECK: saad $2, ($5)
26+
0x72 0xf8 0xc8 0x2a # CHECK: seq $25, $23, $24
27+
0x72 0x10 0x09 0xae # CHECK: seqi $16, $16, 38
28+
0x72 0xf4 0xb8 0x2b # CHECK: sne $23, $23, $20
29+
0x72 0x04 0xb1 0xef # CHECK: snei $4, $16, -313
30+
0x00 0x00 0x01 0x8f # CHECK: sync 6
31+
0x71 0x55 0xa8 0x11 # CHECK: v3mulu $21, $10, $21
32+
0x72 0x70 0x18 0x10 # CHECK: vmm0 $3, $19, $16
33+
0x73 0x66 0xd8 0x0f # CHECK: vmulu $27, $27, $6

‎llvm/test/MC/Mips/cnmipsp/invalid.s

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# Instructions that are invalid.
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#
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# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=octeon+ 2>%t1
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# RUN: FileCheck %s < %t1
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saa $2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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saa $2, $5, $6 # CHECK: :[[@LINE]]:12: error: unexpected token in argument list
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saad $2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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saad $2, $5, $6 # CHECK: :[[@LINE]]:12: error: unexpected token in argument list

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