[AArch64] Add flag setting instructions to scheduling model. (#96880)

Some flag setting instructions (such as ANDS, ADDS, CCMN) were missing
from the V2 scheduling model. This patch adds them in.

Author: Rin Dobrescu

llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td

@@ -1108,12 +1108,17 @@ def : InstRW<[V2Write_1cyc_1B_1R], (instrs BL, BLR)>;
 // ALU, basic
 // ALU, basic, flagset
 def : SchedAlias<WriteI, V2Write_1cyc_1I>;
-def : InstRW<[V2Write_1cyc_1F], (instregex "^(ADC|SBC)S[WX]r$")>;
+def : InstRW<[V2Write_1cyc_1F], (instregex "^(ADD|SUB)S[WX]r[ir]$",
+                        "^(ADC|SBC)S[WX]r$",
+                        "^ANDS[WX]ri$")>;
 def : InstRW<[V2Write_0or1cyc_1I], (instregex "^MOVZ[WX]i$")>;
 
 // ALU, extend and shift
 def : SchedAlias<WriteIEReg, V2Write_2cyc_1M>;
 
+// Conditional compare
+def : InstRW<[V2Write_1cyc_1F], (instregex "^CCM[NP][WX][ir]")>;
+
 // Arithmetic, LSL shift, shift <= 4
 // Arithmetic, flagset, LSL shift, shift <= 4
 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4