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ParkHanbumParkHanbum
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[InstCombine] Add tests
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‎llvm/test/Transforms/InstCombine/select-of-bittest.ll

Lines changed: 210 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,216 @@
33

44
; https://bugs.llvm.org/show_bug.cgi?id=36950
55

6-
; These all should be just and+icmp, there should be no select.
6+
7+
8+
; ====================== AND =======================
9+
define i8 @src_and_bit(i8 %x, i8 %y) {
10+
; CHECK-LABEL: @src_and_bit(
11+
; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], 3
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; CHECK-NEXT: [[AND1:%.*]] = and i8 [[X]], 2
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], 2
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; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i8 [[AND1]], i8 1
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; CHECK-NEXT: ret i8 [[COND]]
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;
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%and = and i8 %x, 3
18+
%and1 = and i8 %x, 2
19+
%and2 = and i8 %and, %x
20+
%cmp = icmp eq i8 %and2, 2
21+
%cond = select i1 %cmp, i8 %and1, i8 1
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ret i8 %cond
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}
24+
define <2 x i8> @src_and_bit_vec(<2 x i8> %x, <2 x i8> %y) {
25+
; CHECK-LABEL: @src_and_bit_vec(
26+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[X:%.*]], <i8 3, i8 3>
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; CHECK-NEXT: [[AND1:%.*]] = and <2 x i8> [[X]], <i8 2, i8 2>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[AND]], <i8 2, i8 2>
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; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[AND1]], <2 x i8> <i8 1, i8 1>
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; CHECK-NEXT: ret <2 x i8> [[COND]]
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;
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%and = and <2 x i8> %x, <i8 3, i8 3>
33+
%and1 = and <2 x i8> %x, <i8 2, i8 2>
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%and2 = and <2 x i8> %and, %x
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%cmp = icmp eq <2 x i8> %and2, <i8 2, i8 2>
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%cond = select <2 x i1> %cmp, <2 x i8> %and1, <2 x i8><i8 1, i8 1>
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ret <2 x i8> %cond
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}
39+
define <2 x i8> @src_and_bit_vec_poison(<2 x i8> %x, <2 x i8> %y) {
40+
; CHECK-LABEL: @src_and_bit_vec_poison(
41+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[X:%.*]], <i8 poison, i8 3>
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; CHECK-NEXT: [[AND1:%.*]] = and <2 x i8> [[X]], <i8 poison, i8 2>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[AND]], <i8 2, i8 2>
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; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[AND1]], <2 x i8> <i8 1, i8 1>
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; CHECK-NEXT: ret <2 x i8> [[COND]]
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;
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%and = and <2 x i8> %x, <i8 poison, i8 3>
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%and1 = and <2 x i8> %x, <i8 poison, i8 2>
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%and2 = and <2 x i8> %and, %x
50+
%cmp = icmp eq <2 x i8> %and2, <i8 2, i8 2>
51+
%cond = select <2 x i1> %cmp, <2 x i8> %and1, <2 x i8><i8 1, i8 1>
52+
ret <2 x i8> %cond
53+
}
54+
define <2 x i8> @src_and_bit_vec_poison2(<2 x i8> %x, <2 x i8> %y) {
55+
; CHECK-LABEL: @src_and_bit_vec_poison2(
56+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[X:%.*]], <i8 poison, i8 3>
57+
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i8> [[X]], <i8 poison, i8 2>
58+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[AND]], <i8 2, i8 2>
59+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[AND1]], <2 x i8> <i8 1, i8 1>
60+
; CHECK-NEXT: ret <2 x i8> [[COND]]
61+
;
62+
%and = and <2 x i8> %x, <i8 poison, i8 3>
63+
%and1 = and <2 x i8> %x, <i8 poison, i8 2>
64+
%and2 = and <2 x i8> %and, %x
65+
%cmp = icmp eq <2 x i8> %and2, <i8 2, i8 2>
66+
%cond = select <2 x i1> %cmp, <2 x i8> %and1, <2 x i8><i8 1, i8 1>
67+
ret <2 x i8> %cond
68+
}
69+
70+
; ====================== OR =======================
71+
define i8 @src_or_bit(i8 %x, i8 %y, i8 %z) {
72+
; CHECK-LABEL: @src_or_bit(
73+
; CHECK-NEXT: [[AND:%.*]] = and i8 [[Z:%.*]], 3
74+
; CHECK-NEXT: [[AND1:%.*]] = shl i8 [[Y:%.*]], 2
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; CHECK-NEXT: [[SHL:%.*]] = and i8 [[AND1]], 12
76+
; CHECK-NEXT: [[OR:%.*]] = or i8 [[SHL]], [[X:%.*]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[OR]], 3
78+
; CHECK-NEXT: [[OR2:%.*]] = or i8 [[AND]], [[X]]
79+
; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i8 [[OR2]], i8 1
80+
; CHECK-NEXT: ret i8 [[COND]]
81+
;
82+
%and = and i8 %z, 3
83+
%and1 = shl i8 %y, 2
84+
%shl = and i8 %and1, 12
85+
%or = or i8 %shl, %x
86+
%cmp = icmp eq i8 %or, 3
87+
%or2 = or i8 %and, %x
88+
%cond = select i1 %cmp, i8 %or2, i8 1
89+
ret i8 %cond
90+
}
91+
define <2 x i8> @src_or_bit_vec(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
92+
; CHECK-LABEL: @src_or_bit_vec(
93+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[Z:%.*]], <i8 3, i8 3>
94+
; CHECK-NEXT: [[AND1:%.*]] = shl <2 x i8> [[Y:%.*]], <i8 2, i8 2>
95+
; CHECK-NEXT: [[SHL:%.*]] = and <2 x i8> [[AND1]], <i8 12, i8 12>
96+
; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[SHL]], [[X:%.*]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[OR]], <i8 3, i8 3>
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; CHECK-NEXT: [[OR2:%.*]] = or <2 x i8> [[AND]], [[X]]
99+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[OR2]], <2 x i8> <i8 1, i8 1>
100+
; CHECK-NEXT: ret <2 x i8> [[COND]]
101+
;
102+
%and = and <2 x i8> %z, <i8 3, i8 3>
103+
%and1 = shl <2 x i8> %y, <i8 2, i8 2>
104+
%shl = and <2 x i8> %and1, <i8 12, i8 12>
105+
%or = or <2 x i8> %shl, %x
106+
%cmp = icmp eq <2 x i8> %or, <i8 3, i8 3>
107+
%or2 = or <2 x i8> %and, %x
108+
%cond = select <2x i1> %cmp, <2 x i8> %or2, <2 x i8> <i8 1, i8 1>
109+
ret <2 x i8> %cond
110+
}
111+
define <2 x i8> @src_or_bit_vec_poison(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
112+
; CHECK-LABEL: @src_or_bit_vec_poison(
113+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[Z:%.*]], <i8 3, i8 poison>
114+
; CHECK-NEXT: [[AND1:%.*]] = shl <2 x i8> [[Y:%.*]], <i8 2, i8 poison>
115+
; CHECK-NEXT: [[SHL:%.*]] = and <2 x i8> [[AND1]], <i8 12, i8 poison>
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; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[SHL]], [[X:%.*]]
117+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[OR]], <i8 3, i8 3>
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; CHECK-NEXT: [[OR2:%.*]] = or <2 x i8> [[AND]], [[X]]
119+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[OR2]], <2 x i8> <i8 1, i8 1>
120+
; CHECK-NEXT: ret <2 x i8> [[COND]]
121+
;
122+
%and = and <2 x i8> %z, <i8 3, i8 poison>
123+
%and1 = shl <2 x i8> %y, <i8 2, i8 poison>
124+
%shl = and <2 x i8> %and1, <i8 12, i8 poison>
125+
%or = or <2 x i8> %shl, %x
126+
%cmp = icmp eq <2 x i8> %or, <i8 3, i8 3>
127+
%or2 = or <2 x i8> %and, %x
128+
%cond = select <2 x i1> %cmp, <2 x i8> %or2, <2 x i8> <i8 1, i8 1>
129+
ret <2 x i8> %cond
130+
}
131+
define <2 x i8> @src_or_bit_vec_poison2(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) {
132+
; CHECK-LABEL: @src_or_bit_vec_poison2(
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; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[Z:%.*]], <i8 poison, i8 3>
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; CHECK-NEXT: [[AND1:%.*]] = shl <2 x i8> [[Y:%.*]], <i8 poison, i8 2>
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; CHECK-NEXT: [[SHL:%.*]] = and <2 x i8> [[AND1]], <i8 poison, i8 12>
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; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[SHL]], [[X:%.*]]
137+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[OR]], <i8 3, i8 3>
138+
; CHECK-NEXT: [[OR2:%.*]] = or <2 x i8> [[AND]], [[X]]
139+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[OR2]], <2 x i8> <i8 1, i8 1>
140+
; CHECK-NEXT: ret <2 x i8> [[COND]]
141+
;
142+
%and = and <2 x i8> %z, <i8 poison, i8 3>
143+
%and1 = shl <2 x i8> %y, <i8 poison, i8 2>
144+
%shl = and <2 x i8> %and1, <i8 poison, i8 12>
145+
%or = or <2 x i8> %shl, %x
146+
%cmp = icmp eq <2 x i8> %or, <i8 3, i8 3>
147+
%or2 = or <2 x i8> %and, %x
148+
%cond = select <2 x i1> %cmp, <2 x i8> %or2, <2 x i8> <i8 1, i8 1>
149+
ret <2 x i8> %cond
150+
}
151+
152+
define i8 @src_xor_bit(i8 %x, i8 %y) {
153+
; CHECK-LABEL: @src_xor_bit(
154+
; CHECK-NEXT: [[AND:%.*]] = and i8 [[Y:%.*]], 12
155+
; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[AND]], [[X:%.*]]
156+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[XOR]], 3
157+
; CHECK-NEXT: [[AND1:%.*]] = and i8 [[X]], 3
158+
; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i8 [[AND1]], i8 1
159+
; CHECK-NEXT: ret i8 [[COND]]
160+
;
161+
%and = and i8 %y, 12
162+
%xor = xor i8 %and, %x
163+
%cmp = icmp eq i8 %xor, 3
164+
%and1 = and i8 %x, 3
165+
%cond = select i1 %cmp, i8 %and1, i8 1
166+
ret i8 %cond
167+
}
168+
define <2 x i8> @src_xor_bit_vec(<2 x i8> %x, <2 x i8> %y) {
169+
; CHECK-LABEL: @src_xor_bit_vec(
170+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[Y:%.*]], <i8 12, i8 12>
171+
; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i8> [[AND]], [[X:%.*]]
172+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[XOR]], <i8 3, i8 3>
173+
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i8> [[X]], <i8 3, i8 3>
174+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[AND1]], <2 x i8> <i8 1, i8 1>
175+
; CHECK-NEXT: ret <2 x i8> [[COND]]
176+
;
177+
%and = and <2 x i8> %y, <i8 12, i8 12>
178+
%xor = xor <2 x i8> %and, %x
179+
%cmp = icmp eq <2 x i8> %xor, <i8 3, i8 3>
180+
%and1 = and <2 x i8> %x, <i8 3, i8 3>
181+
%cond = select <2 x i1> %cmp, <2 x i8> %and1, <2 x i8> <i8 1, i8 1>
182+
ret <2 x i8> %cond
183+
}
184+
define <2 x i8> @src_xor_bit_vec_poison(<2 x i8> %x, <2 x i8> %y) {
185+
; CHECK-LABEL: @src_xor_bit_vec_poison(
186+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[Y:%.*]], <i8 poison, i8 12>
187+
; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i8> [[AND]], [[X:%.*]]
188+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[XOR]], <i8 3, i8 3>
189+
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i8> [[X]], <i8 poison, i8 3>
190+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[AND1]], <2 x i8> <i8 1, i8 1>
191+
; CHECK-NEXT: ret <2 x i8> [[COND]]
192+
;
193+
%and = and <2 x i8> %y, <i8 poison, i8 12>
194+
%xor = xor <2 x i8> %and, %x
195+
%cmp = icmp eq <2 x i8> %xor, <i8 3, i8 3>
196+
%and1 = and <2 x i8> %x, <i8 poison, i8 3>
197+
%cond = select <2 x i1> %cmp, <2 x i8> %and1, <2 x i8> <i8 1, i8 1>
198+
ret <2 x i8> %cond
199+
}
200+
define <2 x i8> @src_xor_bit_vec_poison2(<2 x i8> %x, <2 x i8> %y) {
201+
; CHECK-LABEL: @src_xor_bit_vec_poison2(
202+
; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[Y:%.*]], <i8 poison, i8 12>
203+
; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i8> [[AND]], [[X:%.*]]
204+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[XOR]], <i8 3, i8 3>
205+
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i8> [[X]], <i8 3, i8 3>
206+
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[AND1]], <2 x i8> <i8 1, i8 1>
207+
; CHECK-NEXT: ret <2 x i8> [[COND]]
208+
;
209+
%and = and <2 x i8> %y, <i8 poison, i8 12>
210+
%xor = xor <2 x i8> %and, %x
211+
%cmp = icmp eq <2 x i8> %xor, <i8 3, i8 3>
212+
%and1 = and <2 x i8> %x, <i8 3, i8 3>
213+
%cond = select <2 x i1> %cmp, <2 x i8> %and1, <2 x i8> <i8 1, i8 1>
214+
ret <2 x i8> %cond
215+
}
7216

8217
define i32 @and_lshr_and(i32 %arg) {
9218
; CHECK-LABEL: @and_lshr_and(

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