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Asaf Badouh
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[X86][AVX512] extend vcvtph2ps to support xmm/ymm and sae versions
Differential Revision: http://reviews.llvm.org/D13945 llvm-svn: 251018
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8 files changed

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‎llvm/include/llvm/IR/IntrinsicsX86.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3854,6 +3854,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
38543854
def int_x86_avx512_mask_vcvtph2ps_512 : GCCBuiltin<"__builtin_ia32_vcvtph2ps512_mask">,
38553855
Intrinsic<[llvm_v16f32_ty], [llvm_v16i16_ty, llvm_v16f32_ty,
38563856
llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
3857+
def int_x86_avx512_mask_vcvtph2ps_256 : GCCBuiltin<"__builtin_ia32_vcvtph2ps256_mask">,
3858+
Intrinsic<[llvm_v8f32_ty], [llvm_v8i16_ty, llvm_v8f32_ty,
3859+
llvm_i8_ty], [IntrNoMem]>;
3860+
def int_x86_avx512_mask_vcvtph2ps_128 : GCCBuiltin<"__builtin_ia32_vcvtph2ps128_mask">,
3861+
Intrinsic<[llvm_v4f32_ty], [llvm_v8i16_ty, llvm_v4f32_ty,
3862+
llvm_i8_ty], [IntrNoMem]>;
38573863
def int_x86_avx512_mask_vcvtps2ph_512 : GCCBuiltin<"__builtin_ia32_vcvtps2ph512_mask">,
38583864
Intrinsic<[llvm_v16i16_ty], [llvm_v16f32_ty, llvm_i32_ty,
38593865
llvm_v16i16_ty, llvm_i16_ty], [IntrNoMem]>;

‎llvm/lib/Target/X86/X86InstrAVX512.td

Lines changed: 33 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -5331,14 +5331,39 @@ let Predicates = [HasAVX512] in {
53315331
//===----------------------------------------------------------------------===//
53325332
// Half precision conversion instructions
53335333
//===----------------------------------------------------------------------===//
5334-
multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
5335-
X86MemOperand x86memop> {
5336-
def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
5337-
"vcvtph2ps\t{$src, $dst|$dst, $src}",
5338-
[]>, EVEX;
5339-
let hasSideEffects = 0, mayLoad = 1 in
5340-
def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
5341-
"vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
5334+
multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5335+
X86MemOperand x86memop, PatFrag ld_frag> {
5336+
defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5337+
"vcvtph2ps", "$src", "$src",
5338+
(X86cvtph2ps (_src.VT _src.RC:$src),
5339+
(i32 FROUND_CURRENT))>, T8PD;
5340+
let hasSideEffects = 0, mayLoad = 1 in {
5341+
defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
5342+
"vcvtph2ps", "$src", "$src",
5343+
(X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
5344+
(i32 FROUND_CURRENT))>, T8PD;
5345+
}
5346+
}
5347+
5348+
multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5349+
X86MemOperand x86memop> {
5350+
defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5351+
"vcvtph2ps", "{sae}, $src", "$src, {sae}",
5352+
(X86cvtph2ps (_src.VT _src.RC:$src),
5353+
(i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
5354+
5355+
}
5356+
5357+
let Predicates = [HasAVX512] in {
5358+
defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
5359+
avx512_cvtph2ps_sae<v16f32_info, v16i16x_info, f256mem>,
5360+
EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5361+
let Predicates = [HasVLX] in {
5362+
defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
5363+
loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5364+
defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
5365+
loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5366+
}
53425367
}
53435368

53445369
multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
@@ -5353,19 +5378,13 @@ multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
53535378
"vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
53545379
}
53555380

5356-
defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
5357-
EVEX_CD8<32, CD8VH>;
53585381
defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
53595382
EVEX_CD8<32, CD8VH>;
53605383

53615384
def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
53625385
imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
53635386
(VCVTPS2PHZrr VR512:$src, imm:$rc)>;
53645387

5365-
def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
5366-
(bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
5367-
(VCVTPH2PSZrr VR256X:$src)>;
5368-
53695388
let Defs = [EFLAGS], Predicates = [HasAVX512] in {
53705389
defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
53715390
"ucomiss">, PS, EVEX, VEX_LIG,

‎llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -507,6 +507,12 @@ def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
507507
def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
508508
def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
509509

510+
def X86cvtph2ps : SDNode<"ISD::FP16_TO_FP",
511+
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
512+
SDTCVecEltisVT<0, f32>,
513+
SDTCVecEltisVT<1, i16>,
514+
SDTCisFP<0>, SDTCisInt<2>]> >;
515+
510516
def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
511517
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
512518
SDTCisFP<0>, SDTCisFP<1>,

‎llvm/lib/Target/X86/X86IntrinsicsInfo.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1356,6 +1356,12 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
13561356
X86ISD::VALIGN, 0),
13571357
X86_INTRINSIC_DATA(avx512_mask_valign_q_512, INTR_TYPE_3OP_IMM8_MASK,
13581358
X86ISD::VALIGN, 0),
1359+
X86_INTRINSIC_DATA(avx512_mask_vcvtph2ps_128, INTR_TYPE_1OP_MASK_RM,
1360+
ISD::FP16_TO_FP, 0),
1361+
X86_INTRINSIC_DATA(avx512_mask_vcvtph2ps_256, INTR_TYPE_1OP_MASK_RM,
1362+
ISD::FP16_TO_FP, 0),
1363+
X86_INTRINSIC_DATA(avx512_mask_vcvtph2ps_512, INTR_TYPE_1OP_MASK_RM,
1364+
ISD::FP16_TO_FP, 0),
13591365
X86_INTRINSIC_DATA(avx512_mask_vfmadd_pd_128, FMA_OP_MASK, X86ISD::FMADD, 0),
13601366
X86_INTRINSIC_DATA(avx512_mask_vfmadd_pd_256, FMA_OP_MASK, X86ISD::FMADD, 0),
13611367
X86_INTRINSIC_DATA(avx512_mask_vfmadd_pd_512, FMA_OP_MASK, X86ISD::FMADD,

‎llvm/test/CodeGen/X86/avx512-intrinsics.ll

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -322,10 +322,40 @@ define i64 @test_x86_avx512_cvtsd2usi64(<2 x double> %a0) {
322322
declare i64 @llvm.x86.avx512.cvtsd2usi64(<2 x double>) nounwind readnone
323323

324324
define <16 x float> @test_x86_vcvtph2ps_512(<16 x i16> %a0) {
325+
; CHECK: test_x86_vcvtph2ps_512
325326
; CHECK: vcvtph2ps %ymm0, %zmm0 ## encoding: [0x62,0xf2,0x7d,0x48,0x13,0xc0]
326327
%res = call <16 x float> @llvm.x86.avx512.mask.vcvtph2ps.512(<16 x i16> %a0, <16 x float> zeroinitializer, i16 -1, i32 4)
327328
ret <16 x float> %res
328329
}
330+
331+
define <16 x float> @test_x86_vcvtph2ps_512_sae(<16 x i16> %a0) {
332+
; CHECK: test_x86_vcvtph2ps_512_sae
333+
; CHECK: vcvtph2ps {sae}, %ymm0, %zmm0
334+
%res = call <16 x float> @llvm.x86.avx512.mask.vcvtph2ps.512(<16 x i16> %a0, <16 x float> zeroinitializer, i16 -1, i32 8)
335+
ret <16 x float> %res
336+
}
337+
338+
define <16 x float> @test_x86_vcvtph2ps_512_rrk(<16 x i16> %a0,<16 x float> %a1, i16 %mask) {
339+
; CHECK: test_x86_vcvtph2ps_512_rrk
340+
; CHECK: vcvtph2ps %ymm0, %zmm1 {%k1}
341+
%res = call <16 x float> @llvm.x86.avx512.mask.vcvtph2ps.512(<16 x i16> %a0, <16 x float> %a1, i16 %mask, i32 4)
342+
ret <16 x float> %res
343+
}
344+
345+
define <16 x float> @test_x86_vcvtph2ps_512_sae_rrkz(<16 x i16> %a0, i16 %mask) {
346+
; CHECK: test_x86_vcvtph2ps_512_sae_rrkz
347+
; CHECK: vcvtph2ps {sae}, %ymm0, %zmm0 {%k1} {z}
348+
%res = call <16 x float> @llvm.x86.avx512.mask.vcvtph2ps.512(<16 x i16> %a0, <16 x float> zeroinitializer, i16 %mask, i32 8)
349+
ret <16 x float> %res
350+
}
351+
352+
define <16 x float> @test_x86_vcvtph2ps_512_rrkz(<16 x i16> %a0, i16 %mask) {
353+
; CHECK: test_x86_vcvtph2ps_512_rrkz
354+
; CHECK: vcvtph2ps %ymm0, %zmm0 {%k1} {z}
355+
%res = call <16 x float> @llvm.x86.avx512.mask.vcvtph2ps.512(<16 x i16> %a0, <16 x float> zeroinitializer, i16 %mask, i32 4)
356+
ret <16 x float> %res
357+
}
358+
329359
declare <16 x float> @llvm.x86.avx512.mask.vcvtph2ps.512(<16 x i16>, <16 x float>, i16, i32) nounwind readonly
330360

331361

‎llvm/test/CodeGen/X86/avx512vl-intrinsics.ll

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5269,3 +5269,49 @@ define <2 x i64>@test_int_x86_avx512_pbroadcastq_128(<2 x i64> %x0, <2 x i64> %x
52695269
ret <2 x i64> %res4
52705270
}
52715271

5272+
define <4 x float> @test_x86_vcvtph2ps_128(<8 x i16> %a0) {
5273+
; CHECK: test_x86_vcvtph2ps_128
5274+
; CHECK: vcvtph2ps %xmm0, %xmm0
5275+
%res = call <4 x float> @llvm.x86.avx512.mask.vcvtph2ps.128(<8 x i16> %a0, <4 x float> zeroinitializer, i8 -1)
5276+
ret <4 x float> %res
5277+
}
5278+
5279+
define <4 x float> @test_x86_vcvtph2ps_128_rrk(<8 x i16> %a0,<4 x float> %a1, i8 %mask) {
5280+
; CHECK: test_x86_vcvtph2ps_128_rrk
5281+
; CHECK: vcvtph2ps %xmm0, %xmm1 {%k1}
5282+
%res = call <4 x float> @llvm.x86.avx512.mask.vcvtph2ps.128(<8 x i16> %a0, <4 x float> %a1, i8 %mask)
5283+
ret <4 x float> %res
5284+
}
5285+
5286+
5287+
define <4 x float> @test_x86_vcvtph2ps_128_rrkz(<8 x i16> %a0, i8 %mask) {
5288+
; CHECK: test_x86_vcvtph2ps_128_rrkz
5289+
; CHECK: vcvtph2ps %xmm0, %xmm0 {%k1} {z}
5290+
%res = call <4 x float> @llvm.x86.avx512.mask.vcvtph2ps.128(<8 x i16> %a0, <4 x float> zeroinitializer, i8 %mask)
5291+
ret <4 x float> %res
5292+
}
5293+
5294+
declare <4 x float> @llvm.x86.avx512.mask.vcvtph2ps.128(<8 x i16>, <4 x float>, i8) nounwind readonly
5295+
5296+
define <8 x float> @test_x86_vcvtph2ps_256(<8 x i16> %a0) {
5297+
; CHECK: test_x86_vcvtph2ps_256
5298+
; CHECK: vcvtph2ps %xmm0, %ymm0
5299+
%res = call <8 x float> @llvm.x86.avx512.mask.vcvtph2ps.256(<8 x i16> %a0, <8 x float> zeroinitializer, i8 -1)
5300+
ret <8 x float> %res
5301+
}
5302+
5303+
define <8 x float> @test_x86_vcvtph2ps_256_rrk(<8 x i16> %a0,<8 x float> %a1, i8 %mask) {
5304+
; CHECK: test_x86_vcvtph2ps_256_rrk
5305+
; CHECK: vcvtph2ps %xmm0, %ymm1 {%k1}
5306+
%res = call <8 x float> @llvm.x86.avx512.mask.vcvtph2ps.256(<8 x i16> %a0, <8 x float> %a1, i8 %mask)
5307+
ret <8 x float> %res
5308+
}
5309+
5310+
define <8 x float> @test_x86_vcvtph2ps_256_rrkz(<8 x i16> %a0, i8 %mask) {
5311+
; CHECK: test_x86_vcvtph2ps_256_rrkz
5312+
; CHECK: vcvtph2ps %xmm0, %ymm0 {%k1} {z}
5313+
%res = call <8 x float> @llvm.x86.avx512.mask.vcvtph2ps.256(<8 x i16> %a0, <8 x float> zeroinitializer, i8 %mask)
5314+
ret <8 x float> %res
5315+
}
5316+
5317+
declare <8 x float> @llvm.x86.avx512.mask.vcvtph2ps.256(<8 x i16>, <8 x float>, i8) nounwind readonly

‎llvm/test/MC/X86/avx512-encodings.s

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17857,3 +17857,42 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
1785717857
// CHECK: encoding: [0x62,0xd2,0xfd,0x48,0x7c,0xc8]
1785817858
vpbroadcastq %r8, %zmm1
1785917859

17860+
// CHECK: vcvtph2ps %ymm27, %zmm13
17861+
// CHECK: encoding: [0x62,0x12,0x7d,0x48,0x13,0xeb]
17862+
vcvtph2ps %ymm27, %zmm13
17863+
17864+
// CHECK: vcvtph2ps %ymm27, %zmm13 {%k3}
17865+
// CHECK: encoding: [0x62,0x12,0x7d,0x4b,0x13,0xeb]
17866+
vcvtph2ps %ymm27, %zmm13 {%k3}
17867+
17868+
// CHECK: vcvtph2ps %ymm27, %zmm13 {%k3} {z}
17869+
// CHECK: encoding: [0x62,0x12,0x7d,0xcb,0x13,0xeb]
17870+
vcvtph2ps %ymm27, %zmm13 {%k3} {z}
17871+
17872+
// CHECK: vcvtph2ps {sae}, %ymm27, %zmm13
17873+
// CHECK: encoding: [0x62,0x12,0x7d,0x18,0x13,0xeb]
17874+
vcvtph2ps {sae}, %ymm27, %zmm13
17875+
17876+
// CHECK: vcvtph2ps (%rcx), %zmm13
17877+
// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x13,0x29]
17878+
vcvtph2ps (%rcx), %zmm13
17879+
17880+
// CHECK: vcvtph2ps 291(%rax,%r14,8), %zmm13
17881+
// CHECK: encoding: [0x62,0x32,0x7d,0x48,0x13,0xac,0xf0,0x23,0x01,0x00,0x00]
17882+
vcvtph2ps 291(%rax,%r14,8), %zmm13
17883+
17884+
// CHECK: vcvtph2ps 4064(%rdx), %zmm13
17885+
// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x13,0x6a,0x7f]
17886+
vcvtph2ps 4064(%rdx), %zmm13
17887+
17888+
// CHECK: vcvtph2ps 4096(%rdx), %zmm13
17889+
// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x13,0xaa,0x00,0x10,0x00,0x00]
17890+
vcvtph2ps 4096(%rdx), %zmm13
17891+
17892+
// CHECK: vcvtph2ps -4096(%rdx), %zmm13
17893+
// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x13,0x6a,0x80]
17894+
vcvtph2ps -4096(%rdx), %zmm13
17895+
17896+
// CHECK: vcvtph2ps -4128(%rdx), %zmm13
17897+
// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x13,0xaa,0xe0,0xef,0xff,0xff]
17898+
vcvtph2ps -4128(%rdx), %zmm13

‎llvm/test/MC/X86/x86-64-avx512f_vl.s

Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21811,3 +21811,74 @@ vaddpd {rz-sae}, %zmm2, %zmm1, %zmm1
2181121811
// CHECK: encoding: [0x62,0xc2,0xfd,0x28,0x7c,0xd8]
2181221812
vpbroadcastq %r8, %ymm19
2181321813

21814+
// CHECK: vcvtph2ps %xmm17, %xmm27
21815+
// CHECK: encoding: [0x62,0x22,0x7d,0x08,0x13,0xd9]
21816+
vcvtph2ps %xmm17, %xmm27
21817+
21818+
// CHECK: vcvtph2ps %xmm17, %xmm27 {%k2}
21819+
// CHECK: encoding: [0x62,0x22,0x7d,0x0a,0x13,0xd9]
21820+
vcvtph2ps %xmm17, %xmm27 {%k2}
21821+
21822+
// CHECK: vcvtph2ps %xmm17, %xmm27 {%k2} {z}
21823+
// CHECK: encoding: [0x62,0x22,0x7d,0x8a,0x13,0xd9]
21824+
vcvtph2ps %xmm17, %xmm27 {%k2} {z}
21825+
21826+
// CHECK: vcvtph2ps (%rcx), %xmm27
21827+
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x13,0x19]
21828+
vcvtph2ps (%rcx), %xmm27
21829+
21830+
// CHECK: vcvtph2ps 291(%rax,%r14,8), %xmm27
21831+
// CHECK: encoding: [0x62,0x22,0x7d,0x08,0x13,0x9c,0xf0,0x23,0x01,0x00,0x00]
21832+
vcvtph2ps 291(%rax,%r14,8), %xmm27
21833+
21834+
// CHECK: vcvtph2ps 1016(%rdx), %xmm27
21835+
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x13,0x5a,0x7f]
21836+
vcvtph2ps 1016(%rdx), %xmm27
21837+
21838+
// CHECK: vcvtph2ps 1024(%rdx), %xmm27
21839+
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x13,0x9a,0x00,0x04,0x00,0x00]
21840+
vcvtph2ps 1024(%rdx), %xmm27
21841+
21842+
// CHECK: vcvtph2ps -1024(%rdx), %xmm27
21843+
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x13,0x5a,0x80]
21844+
vcvtph2ps -1024(%rdx), %xmm27
21845+
21846+
// CHECK: vcvtph2ps -1032(%rdx), %xmm27
21847+
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x13,0x9a,0xf8,0xfb,0xff,0xff]
21848+
vcvtph2ps -1032(%rdx), %xmm27
21849+
21850+
// CHECK: vcvtph2ps %xmm22, %ymm30
21851+
// CHECK: encoding: [0x62,0x22,0x7d,0x28,0x13,0xf6]
21852+
vcvtph2ps %xmm22, %ymm30
21853+
21854+
// CHECK: vcvtph2ps %xmm22, %ymm30 {%k7}
21855+
// CHECK: encoding: [0x62,0x22,0x7d,0x2f,0x13,0xf6]
21856+
vcvtph2ps %xmm22, %ymm30 {%k7}
21857+
21858+
// CHECK: vcvtph2ps %xmm22, %ymm30 {%k7} {z}
21859+
// CHECK: encoding: [0x62,0x22,0x7d,0xaf,0x13,0xf6]
21860+
vcvtph2ps %xmm22, %ymm30 {%k7} {z}
21861+
21862+
// CHECK: vcvtph2ps (%rcx), %ymm30
21863+
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x13,0x31]
21864+
vcvtph2ps (%rcx), %ymm30
21865+
21866+
// CHECK: vcvtph2ps 291(%rax,%r14,8), %ymm30
21867+
// CHECK: encoding: [0x62,0x22,0x7d,0x28,0x13,0xb4,0xf0,0x23,0x01,0x00,0x00]
21868+
vcvtph2ps 291(%rax,%r14,8), %ymm30
21869+
21870+
// CHECK: vcvtph2ps 2032(%rdx), %ymm30
21871+
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x13,0x72,0x7f]
21872+
vcvtph2ps 2032(%rdx), %ymm30
21873+
21874+
// CHECK: vcvtph2ps 2048(%rdx), %ymm30
21875+
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x13,0xb2,0x00,0x08,0x00,0x00]
21876+
vcvtph2ps 2048(%rdx), %ymm30
21877+
21878+
// CHECK: vcvtph2ps -2048(%rdx), %ymm30
21879+
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x13,0x72,0x80]
21880+
vcvtph2ps -2048(%rdx), %ymm30
21881+
21882+
// CHECK: vcvtph2ps -2064(%rdx), %ymm30
21883+
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x13,0xb2,0xf0,0xf7,0xff,0xff]
21884+
vcvtph2ps -2064(%rdx), %ymm30

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