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[AggressiveInstCombine] Update tests to use opaque pointers (NFC)
Update performed using (without manual fixup): https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34
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‎llvm/test/Transforms/AggressiveInstCombine/funnel.ll

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -442,7 +442,7 @@ end:
442442
; being cautious not to cause a potential perf pessimization for
443443
; targets that do not have a fshate instruction.
444444

445-
define i32 @could_be_fshr(i32 %a, i32 %b, i32 %c, i32* %p) {
445+
define i32 @could_be_fshr(i32 %a, i32 %b, i32 %c, ptr %p) {
446446
; CHECK-LABEL: @could_be_fshr(
447447
; CHECK-NEXT: entry:
448448
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
@@ -452,7 +452,7 @@ define i32 @could_be_fshr(i32 %a, i32 %b, i32 %c, i32* %p) {
452452
; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[A:%.*]], [[SUB]]
453453
; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[B:%.*]], [[C]]
454454
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
455-
; CHECK-NEXT: store i32 [[OR]], i32* [[P:%.*]], align 4
455+
; CHECK-NEXT: store i32 [[OR]], ptr [[P:%.*]], align 4
456456
; CHECK-NEXT: br label [[END]]
457457
; CHECK: end:
458458
; CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[B]], [[ENTRY:%.*]] ], [ [[OR]], [[FSHBB]] ]
@@ -467,7 +467,7 @@ fshbb:
467467
%shl = shl i32 %a, %sub
468468
%shr = lshr i32 %b, %c
469469
%or = or i32 %shl, %shr
470-
store i32 %or, i32* %p
470+
store i32 %or, ptr %p
471471
br label %end
472472

473473
end:
@@ -484,13 +484,13 @@ declare i32 @f(...)
484484
define i32 @PR48068() {
485485
; CHECK-LABEL: @PR48068(
486486
; CHECK-NEXT: entry:
487-
; CHECK-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @i to i32 ()*)()
488-
; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
487+
; CHECK-NEXT: [[CALL:%.*]] = call i32 @i()
488+
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4
489489
; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0
490490
; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
491491
; CHECK: if.then:
492492
; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CALL]], [[TMP0]]
493-
; CHECK-NEXT: [[CALL_I:%.*]] = call i32 bitcast (i32 (...)* @f to i32 ()*)()
493+
; CHECK-NEXT: [[CALL_I:%.*]] = call i32 @f()
494494
; CHECK-NEXT: [[SUB_I:%.*]] = sub nsw i32 32, [[TMP0]]
495495
; CHECK-NEXT: [[SHR_I:%.*]] = lshr i32 [[CALL_I]], [[SUB_I]]
496496
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], [[SHR_I]]
@@ -500,14 +500,14 @@ define i32 @PR48068() {
500500
; CHECK-NEXT: ret i32 [[H_0]]
501501
;
502502
entry:
503-
%call = call i32 bitcast (i32 (...)* @i to i32 ()*)()
504-
%0 = load i32, i32* @a, align 4
503+
%call = call i32 @i()
504+
%0 = load i32, ptr @a, align 4
505505
%tobool.not = icmp eq i32 %0, 0
506506
br i1 %tobool.not, label %if.end, label %if.then
507507

508508
if.then: ; preds = %entry
509509
%shl = shl i32 %call, %0
510-
%call.i = call i32 bitcast (i32 (...)* @f to i32 ()*)()
510+
%call.i = call i32 @f()
511511
%sub.i = sub nsw i32 32, %0
512512
%shr.i = lshr i32 %call.i, %sub.i
513513
%or = or i32 %shl, %shr.i

‎llvm/test/Transforms/AggressiveInstCombine/pr50555.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,31 +1,31 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
22
; RUN: opt < %s -passes=aggressive-instcombine -S | FileCheck %s
33

4-
define void @trunc_one_add(i16* %a, i8 %b) {
4+
define void @trunc_one_add(ptr %a, i8 %b) {
55
; CHECK-LABEL: @trunc_one_add(
66
; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[B:%.*]] to i16
77
; CHECK-NEXT: [[SHR:%.*]] = lshr i16 [[ZEXT]], 1
88
; CHECK-NEXT: [[ADD:%.*]] = add i16 [[ZEXT]], [[SHR]]
9-
; CHECK-NEXT: store i16 [[ADD]], i16* [[A:%.*]], align 2
9+
; CHECK-NEXT: store i16 [[ADD]], ptr [[A:%.*]], align 2
1010
; CHECK-NEXT: ret void
1111
;
1212
%zext = zext i8 %b to i32
1313
%shr = lshr i32 %zext, 1
1414
%add = add nsw i32 %zext, %shr
1515
%trunc = trunc i32 %add to i16
16-
store i16 %trunc, i16* %a, align 2
16+
store i16 %trunc, ptr %a, align 2
1717
ret void
1818
}
1919

20-
define void @trunc_two_adds(i16* %a, i8 %b, i8 %c) {
20+
define void @trunc_two_adds(ptr %a, i8 %b, i8 %c) {
2121
; CHECK-LABEL: @trunc_two_adds(
2222
; CHECK-NEXT: [[ZEXT1:%.*]] = zext i8 [[B:%.*]] to i16
2323
; CHECK-NEXT: [[ZEXT2:%.*]] = zext i8 [[C:%.*]] to i16
2424
; CHECK-NEXT: [[ADD1:%.*]] = add i16 [[ZEXT1]], [[ZEXT2]]
2525
; CHECK-NEXT: [[SHR1:%.*]] = lshr i16 [[ADD1]], 1
2626
; CHECK-NEXT: [[ADD2:%.*]] = add i16 [[ADD1]], [[SHR1]]
2727
; CHECK-NEXT: [[SHR2:%.*]] = lshr i16 [[ADD2]], 2
28-
; CHECK-NEXT: store i16 [[SHR2]], i16* [[A:%.*]], align 2
28+
; CHECK-NEXT: store i16 [[SHR2]], ptr [[A:%.*]], align 2
2929
; CHECK-NEXT: ret void
3030
;
3131
%zext1 = zext i8 %b to i32
@@ -35,6 +35,6 @@ define void @trunc_two_adds(i16* %a, i8 %b, i8 %c) {
3535
%add2 = add nuw nsw i32 %add1, %shr1
3636
%shr2 = lshr i32 %add2, 2
3737
%trunc = trunc i32 %shr2 to i16
38-
store i16 %trunc, i16* %a, align 2
38+
store i16 %trunc, ptr %a, align 2
3939
ret void
4040
}

‎llvm/test/Transforms/AggressiveInstCombine/rotate.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -437,7 +437,7 @@ end:
437437
; being cautious not to cause a potential perf pessimization for
438438
; targets that do not have a rotate instruction.
439439

440-
define i32 @could_be_rotr(i32 %a, i32 %b, i32* %p) {
440+
define i32 @could_be_rotr(i32 %a, i32 %b, ptr %p) {
441441
; CHECK-LABEL: @could_be_rotr(
442442
; CHECK-NEXT: entry:
443443
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[B:%.*]], 0
@@ -447,7 +447,7 @@ define i32 @could_be_rotr(i32 %a, i32 %b, i32* %p) {
447447
; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[A:%.*]], [[SUB]]
448448
; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[A]], [[B]]
449449
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
450-
; CHECK-NEXT: store i32 [[OR]], i32* [[P:%.*]], align 4
450+
; CHECK-NEXT: store i32 [[OR]], ptr [[P:%.*]], align 4
451451
; CHECK-NEXT: br label [[END]]
452452
; CHECK: end:
453453
; CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[A]], [[ENTRY:%.*]] ], [ [[OR]], [[ROTBB]] ]
@@ -462,7 +462,7 @@ rotbb:
462462
%shl = shl i32 %a, %sub
463463
%shr = lshr i32 %a, %b
464464
%or = or i32 %shl, %shr
465-
store i32 %or, i32* %p
465+
store i32 %or, ptr %p
466466
br label %end
467467

468468
end:

‎llvm/test/Transforms/AggressiveInstCombine/trunc_ashr.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,7 @@ define i32 @ashr_check_no_overflow(i32 %x, i16 %amt) {
103103
ret i32 %trunc
104104
}
105105

106-
define void @ashr_big_dag(i16* %a, i8 %b, i8 %c) {
106+
define void @ashr_big_dag(ptr %a, i8 %b, i8 %c) {
107107
; CHECK-LABEL: @ashr_big_dag(
108108
; CHECK-NEXT: [[ZEXT1:%.*]] = zext i8 [[B:%.*]] to i16
109109
; CHECK-NEXT: [[ZEXT2:%.*]] = zext i8 [[C:%.*]] to i16
@@ -113,7 +113,7 @@ define void @ashr_big_dag(i16* %a, i8 %b, i8 %c) {
113113
; CHECK-NEXT: [[ADD2:%.*]] = add i16 [[ADD1]], [[SHR1]]
114114
; CHECK-NEXT: [[SFT2:%.*]] = and i16 [[ADD2]], 7
115115
; CHECK-NEXT: [[SHR2:%.*]] = ashr i16 [[ADD2]], [[SFT2]]
116-
; CHECK-NEXT: store i16 [[SHR2]], i16* [[A:%.*]], align 2
116+
; CHECK-NEXT: store i16 [[SHR2]], ptr [[A:%.*]], align 2
117117
; CHECK-NEXT: ret void
118118
;
119119
%zext1 = zext i8 %b to i32
@@ -125,7 +125,7 @@ define void @ashr_big_dag(i16* %a, i8 %b, i8 %c) {
125125
%sft2 = and i32 %add2, 7
126126
%shr2 = ashr i32 %add2, %sft2
127127
%trunc = trunc i32 %shr2 to i16
128-
store i16 %trunc, i16* %a, align 2
128+
store i16 %trunc, ptr %a, align 2
129129
ret void
130130
}
131131

‎llvm/test/Transforms/AggressiveInstCombine/trunc_lshr.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ define i32 @lshr_check_no_overflow(i32 %x, i16 %amt) {
8787
ret i32 %trunc
8888
}
8989

90-
define void @lshr_big_dag(i16* %a, i8 %b, i8 %c) {
90+
define void @lshr_big_dag(ptr %a, i8 %b, i8 %c) {
9191
; CHECK-LABEL: @lshr_big_dag(
9292
; CHECK-NEXT: [[ZEXT1:%.*]] = zext i8 [[B:%.*]] to i16
9393
; CHECK-NEXT: [[ZEXT2:%.*]] = zext i8 [[C:%.*]] to i16
@@ -97,7 +97,7 @@ define void @lshr_big_dag(i16* %a, i8 %b, i8 %c) {
9797
; CHECK-NEXT: [[ADD2:%.*]] = add i16 [[ADD1]], [[SHR1]]
9898
; CHECK-NEXT: [[SFT2:%.*]] = and i16 [[ADD2]], 7
9999
; CHECK-NEXT: [[SHR2:%.*]] = lshr i16 [[ADD2]], [[SFT2]]
100-
; CHECK-NEXT: store i16 [[SHR2]], i16* [[A:%.*]], align 2
100+
; CHECK-NEXT: store i16 [[SHR2]], ptr [[A:%.*]], align 2
101101
; CHECK-NEXT: ret void
102102
;
103103
%zext1 = zext i8 %b to i32
@@ -109,7 +109,7 @@ define void @lshr_big_dag(i16* %a, i8 %b, i8 %c) {
109109
%sft2 = and i32 %add2, 7
110110
%shr2 = lshr i32 %add2, %sft2
111111
%trunc = trunc i32 %shr2 to i16
112-
store i16 %trunc, i16* %a, align 2
112+
store i16 %trunc, ptr %a, align 2
113113
ret void
114114
}
115115

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