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[GISel][RISCV][AMDGPU] Add G_SHL, G_LSHR, G_ASHR to binop_left_to_zero. (#115089)
Shifting 0 by any amount is still zero.
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4 files changed

+38
-53
lines changed

4 files changed

+38
-53
lines changed

‎llvm/include/llvm/Target/GlobalISel/Combine.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -566,7 +566,8 @@ def binop_same_val: GICombineRule<
566566
// Fold (0 op x) - > 0
567567
def binop_left_to_zero: GICombineRule<
568568
(defs root:$root),
569-
(match (wip_match_opcode G_SDIV, G_UDIV, G_SREM, G_UREM):$root,
569+
(match (wip_match_opcode G_SHL, G_LSHR, G_ASHR, G_SDIV, G_UDIV, G_SREM,
570+
G_UREM):$root,
570571
[{ return Helper.matchOperandIsZero(*${root}, 1); }]),
571572
(apply [{ Helper.replaceSingleDefInstWithOperand(*${root}, 1); }])
572573
>;

‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -348,14 +348,14 @@ body: |
348348
; GFX6-LABEL: name: do_not_shl_s32_zero_by_16_from_zext_s16
349349
; GFX6: liveins: $vgpr0
350350
; GFX6-NEXT: {{ $}}
351-
; GFX6-NEXT: %shl:_(s32) = G_CONSTANT i32 0
352-
; GFX6-NEXT: $vgpr0 = COPY %shl(s32)
351+
; GFX6-NEXT: %extend:_(s32) = G_CONSTANT i32 0
352+
; GFX6-NEXT: $vgpr0 = COPY %extend(s32)
353353
;
354354
; GFX9-LABEL: name: do_not_shl_s32_zero_by_16_from_zext_s16
355355
; GFX9: liveins: $vgpr0
356356
; GFX9-NEXT: {{ $}}
357-
; GFX9-NEXT: %shl:_(s32) = G_CONSTANT i32 0
358-
; GFX9-NEXT: $vgpr0 = COPY %shl(s32)
357+
; GFX9-NEXT: %extend:_(s32) = G_CONSTANT i32 0
358+
; GFX9-NEXT: $vgpr0 = COPY %extend(s32)
359359
%zero:_(s16) = G_CONSTANT i16 0
360360
%extend:_(s32) = G_ZEXT %zero:_(s16)
361361
%shiftamt:_(s16) = G_CONSTANT i16 16

‎llvm/test/CodeGen/AMDGPU/fptoi.i128.ll

Lines changed: 32 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -270,14 +270,12 @@ define i128 @fptosi_f64_to_i128(double %x) {
270270
; GISEL-NEXT: s_andn2_saveexec_b64 s[8:9], s[16:17]
271271
; GISEL-NEXT: s_cbranch_execz .LBB0_6
272272
; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12
273-
; GISEL-NEXT: v_sub_co_u32_e32 v6, vcc, 0x433, v6
274-
; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v6
275-
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v6, v[4:5]
276-
; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, 0
277-
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6
278-
; GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
279-
; GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
280-
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
273+
; GISEL-NEXT: v_sub_co_u32_e32 v2, vcc, 0x433, v6
274+
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v2, v[4:5]
275+
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
276+
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
277+
; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
278+
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
281279
; GISEL-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
282280
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v4, v10, 0
283281
; GISEL-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
@@ -640,14 +638,12 @@ define i128 @fptoui_f64_to_i128(double %x) {
640638
; GISEL-NEXT: s_andn2_saveexec_b64 s[8:9], s[16:17]
641639
; GISEL-NEXT: s_cbranch_execz .LBB1_6
642640
; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12
643-
; GISEL-NEXT: v_sub_co_u32_e32 v6, vcc, 0x433, v6
644-
; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v6
645-
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v6, v[4:5]
646-
; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, 0
647-
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6
648-
; GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
649-
; GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
650-
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
641+
; GISEL-NEXT: v_sub_co_u32_e32 v2, vcc, 0x433, v6
642+
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v2, v[4:5]
643+
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
644+
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
645+
; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
646+
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
651647
; GISEL-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
652648
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v4, v10, 0
653649
; GISEL-NEXT: v_cndmask_b32_e32 v5, v1, v5, vcc
@@ -1003,13 +999,11 @@ define i128 @fptosi_f32_to_i128(float %x) {
1003999
; GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[16:17]
10041000
; GISEL-NEXT: s_cbranch_execz .LBB2_6
10051001
; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12
1006-
; GISEL-NEXT: v_sub_co_u32_e32 v3, vcc, 0x96, v6
1007-
; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v3
1008-
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v3, v[4:5]
1009-
; GISEL-NEXT: v_lshrrev_b64 v[1:2], v2, 0
1010-
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3
1011-
; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
1012-
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
1002+
; GISEL-NEXT: v_sub_co_u32_e32 v2, vcc, 0x96, v6
1003+
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v2, v[4:5]
1004+
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
1005+
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
1006+
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
10131007
; GISEL-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
10141008
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v4, v9, 0
10151009
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[8:9], v4, v10, 0
@@ -1360,13 +1354,11 @@ define i128 @fptoui_f32_to_i128(float %x) {
13601354
; GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[16:17]
13611355
; GISEL-NEXT: s_cbranch_execz .LBB3_6
13621356
; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12
1363-
; GISEL-NEXT: v_sub_co_u32_e32 v3, vcc, 0x96, v6
1364-
; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v3
1365-
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v3, v[4:5]
1366-
; GISEL-NEXT: v_lshrrev_b64 v[1:2], v2, 0
1367-
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3
1368-
; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
1369-
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
1357+
; GISEL-NEXT: v_sub_co_u32_e32 v2, vcc, 0x96, v6
1358+
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v2, v[4:5]
1359+
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
1360+
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
1361+
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
13701362
; GISEL-NEXT: v_cndmask_b32_e32 v4, v0, v4, vcc
13711363
; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v4, v9, 0
13721364
; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[8:9], v4, v10, 0
@@ -1740,13 +1732,11 @@ define i128 @fptosi_bf16_to_i128(bfloat %x) {
17401732
; GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[16:17]
17411733
; GISEL-NEXT: s_cbranch_execz .LBB6_6
17421734
; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12
1743-
; GISEL-NEXT: v_sub_co_u32_e32 v3, vcc, 0x86, v5
1744-
; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v3
1745-
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v3, v[7:8]
1746-
; GISEL-NEXT: v_lshrrev_b64 v[1:2], v2, 0
1747-
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3
1748-
; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
1749-
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
1735+
; GISEL-NEXT: v_sub_co_u32_e32 v2, vcc, 0x86, v5
1736+
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v2, v[7:8]
1737+
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
1738+
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
1739+
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
17501740
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
17511741
; GISEL-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v9
17521742
; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v1
@@ -2091,13 +2081,11 @@ define i128 @fptoui_bf16_to_i128(bfloat %x) {
20912081
; GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[16:17]
20922082
; GISEL-NEXT: s_cbranch_execz .LBB7_6
20932083
; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12
2094-
; GISEL-NEXT: v_sub_co_u32_e32 v3, vcc, 0x86, v5
2095-
; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v3
2096-
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v3, v[7:8]
2097-
; GISEL-NEXT: v_lshrrev_b64 v[1:2], v2, 0
2098-
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3
2099-
; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
2100-
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
2084+
; GISEL-NEXT: v_sub_co_u32_e32 v2, vcc, 0x86, v5
2085+
; GISEL-NEXT: v_lshrrev_b64 v[0:1], v2, v[7:8]
2086+
; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2
2087+
; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
2088+
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
21012089
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
21022090
; GISEL-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v9
21032091
; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v1

‎llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -156,18 +156,14 @@ define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
156156
; RV32I-NEXT: andi a0, a0, 255
157157
; RV32I-NEXT: andi a1, a2, 255
158158
; RV32I-NEXT: slli a2, a1, 8
159-
; RV32I-NEXT: slli a3, zero, 8
160159
; RV32I-NEXT: srli a1, a1, 24
161-
; RV32I-NEXT: or a1, a3, a1
162160
; RV32I-NEXT: or a0, a2, a0
163161
; RV32I-NEXT: ret
164162
;
165163
; RV32ZBKB-LABEL: packh_i64_2:
166164
; RV32ZBKB: # %bb.0:
167165
; RV32ZBKB-NEXT: andi a1, a2, 255
168-
; RV32ZBKB-NEXT: slli a3, zero, 8
169166
; RV32ZBKB-NEXT: srli a1, a1, 24
170-
; RV32ZBKB-NEXT: or a1, a3, a1
171167
; RV32ZBKB-NEXT: packh a0, a0, a2
172168
; RV32ZBKB-NEXT: ret
173169
%and = and i64 %a, 255

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