@@ -198,7 +198,7 @@ static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) {
198
198
return (CC == CallingConv::X86_VectorCall || CC == CallingConv::X86_FastCall);
199
199
}
200
200
201
- void CCState::getRemainingRegParmsForType (SmallVectorImpl<MCPhysReg > &Regs,
201
+ void CCState::getRemainingRegParmsForType (SmallVectorImpl<MCRegister > &Regs,
202
202
MVT VT, CCAssignFn Fn) {
203
203
uint64_t SavedStackSize = StackSize;
204
204
Align SavedMaxStackArgAlign = MaxStackArgAlign;
@@ -227,7 +227,7 @@ void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs,
227
227
assert (NumLocs < Locs.size () && " CC assignment failed to add location" );
228
228
for (unsigned I = NumLocs, E = Locs.size (); I != E; ++I)
229
229
if (Locs[I].isRegLoc ())
230
- Regs.push_back (MCPhysReg ( Locs[I].getLocReg () ));
230
+ Regs.push_back (Locs[I].getLocReg ());
231
231
232
232
// Clear the assigned values and stack memory. We leave the registers marked
233
233
// as allocated so that future queries don't return the same registers, i.e.
@@ -247,11 +247,11 @@ void CCState::analyzeMustTailForwardedRegisters(
247
247
SaveAndRestore SavedMustTail (AnalyzingMustTailForwardedRegs, true );
248
248
249
249
for (MVT RegVT : RegParmTypes) {
250
- SmallVector<MCPhysReg , 8 > RemainingRegs;
250
+ SmallVector<MCRegister , 8 > RemainingRegs;
251
251
getRemainingRegParmsForType (RemainingRegs, RegVT, Fn);
252
252
const TargetLowering *TL = MF.getSubtarget ().getTargetLowering ();
253
253
const TargetRegisterClass *RC = TL->getRegClassFor (RegVT);
254
- for (MCPhysReg PReg : RemainingRegs) {
254
+ for (MCRegister PReg : RemainingRegs) {
255
255
Register VReg = MF.addLiveIn (PReg, RC);
256
256
Forwards.push_back (ForwardedRegister (VReg, PReg, RegVT));
257
257
}
0 commit comments